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US 7,888,202 B1Granted
Method and apparatus for reducing parasitic capacitance
AssigneeXilinx, Inc.
InventorsFiras N. Abughazaleh, Brian T. Brunn
Life of this patent
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Abstract
A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.
Claims7
A method for providing a low parasitic capacitance device, comprising:
- forming a blocked portion on a substrate;
- forming a P-well around the blocked portion on the substrate;
- wherein formation of a P-well is prevented in the blocked portion of the substrate;
- wherein resistivity of the blocked portion of the substrate is higher than resistivity of the P-well and equal to resistivity of the substrate;
- and
- forming an electronic device above the blocked portion, wherein the blocked portion includes a series resistance to substrate ground to reduce parasitic capacitance of the electronic device;
- wherein the electronic device comprises a signal coupling capacitor;
- wherein the blocked portion includes a portion extending beyond a periphery of the signal coupling capacitor;
- and
- wherein a dimension of the portion is selected to provide a predetermined series resistance between a ground terminal at the substrate and a parasitic capacitance of the signal coupling capacitor.
7 more elements
Dependencies are inferred from the claim text.