Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYee-Chia Yeo, Fu-Liang Yang, Chenming Hu
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Abstract
A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.
Claims20
A method of forming a SRAM cell, the method comprising:
- providing a silicon-on-insulator substrate, said substrate comprising a silicon layer overlying an insulator layer;
- defining at least one active region in the silicon layer;
- forming a gate dielectric layer in the active region;
- forming a plurality of gate electrodes overlying the gate dielectric layer;
- and
- forming source and drain regions adjacent to the plurality of gate electrodes to form a fully depleted transistor and a partially depleted transistor as two transistors of the SRAM cell, wherein the fully depleted transistor has a greater channel length than the partially depleted transistor.
A method of forming a SRAM cell, the method comprising:
- providing a silicon-on-insulator substrate, said substrate comprising a silicon layer overlying an insulator layer;
- forming one or more active regions within the substrate, at least one of the one or more active regions having a first section with a first width and a second section with a second width, the first width being different than the second width;
- forming a fully depleted pass-gate transistor by a method comprising:
- forming a gate dielectric layer over the one or more active regions;
- forming a gate electrode layer over the gate dielectric layer;
- patterning the gate electrode layer to form a first gate electrode in the first section of the at least one of the one or more active regions, wherein the first gate electrode has a first gate length;
- and
- forming first source and drain regions of opposing sides of the first gate electrode;
- and
- forming a partially depleted transistor by a method comprising:
- patterning the gate electrode layer to form a second gate electrode in the second section of the at least one of the one or more active regions, wherein the second gate electrode has a second gate length smaller than the first gate length;
- and
- forming second source and drain regions on opposing sides of the second gate electrode.
A method for forming an SRAM memory array, the method comprising:
- providing a substrate, said substrate comprising a semiconductor layer overlying an insulator layer;
- defining a plurality of active regions in the silicon layer;
- forming a plurality of SRAM memory cells, each cell formed by:
- forming a gate dielectric layer in at least one of the plurality of active regions;
- forming a plurality of gate electrodes overlying the gate dielectric layer;
- and
- forming first source and drain regions adjacent to respective ones of the plurality of gate electrodes to form a fully depleted FinFET transistor, the fully depleted FinFET transistor having a first channel length;
- forming second source and drain regions adjacent to respective ones of the plurality of gate electrodes to form a partially depleted transistor, the partially depleted transistor having a second channel length that is less than the first channel length;
- forming a plurality of complementary bit line pairs connected to respective ones of the plurality of SRAM memory cells;
- and
- forming a plurality of word lines connected to respective ones of the plurality of SRAM memory cells.
Dependencies are inferred from the claim text.