Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region

A method for fabricating a semiconductor device comprising:

• forming a device isolation region on a semiconductor substrate to define a cell array region and a peripheral circuit region;
• forming a first gate in the cell array region, a second gate in the peripheral circuit region, and a third gate in the peripheral circuit region;
• implanting first impurity ions of a low concentration into a first portion of the semiconductor substrate adjacent to the second and third gates, using the second and third gates as a mask, to form a first impurity diffusion region of a first conductivity type;
• forming first gate spacers on lateral sides of the first, second, and third gates;
• implanting second impurity ions of a low concentration into a second portion of the semiconductor substrate adjacent to the first gate and first gate spacers on the lateral sides of the first gate, using the first gate and first gate spacers as a mask, to form a second impurity diffusion region of a first conductivity type;
• implanting third impurity ions of a low concentration into a third portion of the semiconductor substrate adjacent to the third gate and the first gate spacers on the lateral side of the third gate, using the third gate and first gate spacers as a mask, to form a third impurity diffusion region of a second conductivity type;
• forming an insulating layer over the semiconductor substrate, first through third gates, and first gate spacers;
• etching the insulating layer in the peripheral region to form second gate spacers adjacent to the first spacers on the lateral side of the second and third gates, respectively;
• implanting fourth impurity ions of a high concentration into a fourth portion of the semiconductor substrate adjacent to the second gate and the second spacers on the lateral sides of the first spacers of the second gate, using the second gate and the first and second spacers as a mask, to form a fourth impurity diffusion region of a first conductivity type;
• and
• implanting fifth impurity ions of a high concentration into a fifth portion of the semiconductor substrate adjacent to the third gate and the second spacers on the lateral side of the third gate, using the third gate and first and second spacers as a mask, to form a fifth impurity diffusion region of a second conductivity type.