Process for forming integrated circuits with both split gate and common gate FinFET transistors

A method of forming an integrated circuit, comprising:

• providing a substrate having a semiconductor surface;
• forming a plurality of taller fins and a plurality of shorter fins by patterning the semiconductor surface;
• forming a layer of gate dielectric material over tops and sides of both the taller fin and the shorter fin;
• forming a layer of gate electrode material over the layer of gate dielectric material over the tops and sides of both the taller fin and the shorter fin;
• planarizing the layer of gate electrode material to remove the gate electrode material over the top of the taller fin, leaving at least a portion of the gate electrode material over the top between the sides of the shorter fin;
• and
• patterning the planarized layer of gate electrode material to form a split gate structure on the sides of the taller fin and a common gate structure on the top and sides of the shorter fin.

A method of forming an integrated circuit, comprising:

• providing a substrate having a silicon surface over an insulating layer;
• forming a plurality of taller fins and a plurality of shorter fins by selectively etching the silicon surface;
• forming a layer of gate dielectric material over tops and sides of both the taller fin and the shorter fin;
• forming a layer of gate electrode material comprising polysilicon over the layer of gate dielectric material over the tops and sides of both the taller fin and the shorter fin;
• using chemical-mechanical polishing, planarizing the layer of gate electrode material to remove the gate electrode material over the top of the taller fin, leaving at least a portion of the gate electrode material over the top between the sides of the shorter fin;
• and
• selectively etching the planarized layer of gate electrode material to form gate structure on the sides of the taller fin and on the top and sides of the shorter fin.