Embedded chip package process
AssigneeUnimicron Technology Corp.
InventorDavid C. H. Cheng
Life of this patent
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Abstract
An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.
Claims12
An embedded chip package process, comprising:
- providing a first substrate, wherein the first substrate has a first patterned circuit layer thereon and the first patterned circuit layer has at least a first bonding pad, and a first chip is disposed on the first bonding pad and electrically connected to the first patterned circuit layer by performing a flip-chip bonding process;
- providing a second substrate, wherein the second substrate has a second patterned circuit layer thereon and the second patterned circuit layer has at least a second bonding pad,;
- covering a dielectric material layer over the first patterned circuit layer and the first chip;
- performing a compression process to cover the second substrate over the dielectric material layer and embed the second patterned circuit layer of the second substrate into the dielectric material layer;
- performing a curing process to cure the dielectric material layer after the step of performing the compression process;
- removing the first substrate and the second substrate after the step of performing the curing process;
- and
- forming at least a conductive through hole through the dielectric material layer to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of removing the first substrate and the second substrate.
Dependencies are inferred from the claim text.