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US 7,884,743 B2Granted
Arithmetic decoding device
AssigneeSony Corporation
InventorsHiroaki Sakaguchi, Hiroshi Yoshikawa
Life of this patent
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Abstract
Disclosed herein is an arithmetic decoding device including: an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol; a plurality of arithmetic registers configured to supply the context variable to the arithmetic decoding unit and retain a result of operation by the arithmetic decoding unit; and a plurality of save registers configured to save contents retained in the arithmetic registers.
Claims9
An arithmetic decoding device comprising:
- an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol;
- a plurality of arithmetic registers configured to supply said context variable to said arithmetic decoding unit and retain a result of operation by said arithmetic decoding unit;
- and
- a plurality of save registers configured to save contents retained in said arithmetic registers, wherein said plurality of save registers save only context variables relating to predetermined syntax elements among said context variables.
1 more element
An arithmetic decoding device comprising:
- an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol;
- a plurality of arithmetic registers configured to supply said context variable to said arithmetic decoding unit and retain a result of operation by said arithmetic decoding unit:
- and
- a plurality of save registers configured to save contents retained in said arithmetic registers, wherein each of said plurality of arithmetic registers and said plurality of save registers is a register of a 128-bit width and stores 16 context variables with one context variable of 7 bits assigned to each unit of 8 bits, and one or two context variables are stored with 16 bits obtained by collecting one surplus bit of each unit of 8 bits as a surplus register.
1 more element
Dependencies are inferred from the claim text.