Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias

A method comprising:

• providing a body and forming a first metal pad layer on a first surface thereof;
• forming a second metal pad layer in contact with the first metal pad layer, wherein the first and second metal pad layers are formed so that the first metal pad layer includes a plurality of spaced apart metal pads and the second metal pad layer includes a plurality of spaced apart metal pads, the second metal pad layer having a denser pitch than the first metal pad layer;
• forming a dielectric layer between the metal pads in the first metal pad layer and between the metal pads in the second metal pad layer;
• after forming the first and second metal pad layers and the dielectric layer, thinning the body from a second surface thereof, the second surface opposite the first surface;
• after thinning the body, forming a plurality of vias extending through the body from a second surface thereof, the vias exposing the first metal pad layer;
• forming an insulating layer on sidewalls of the vias and on the second surface;
• forming an electrically conductive layer on the insulating layer and on the exposed surface of the first metal pad layer;
• and
• coupling a plurality of elements to the second metal pad layer and coupling the electrically conductive layer to a substrate, the body being positioned between the elements and the substrate.