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US 7,882,456 B2Granted
Optical lithography correction process
AssigneeCadence Design Systems, Inc.
InventorFranz Xaver Zach
Life of this patent
Estimating the term…
Abstract
A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
Claims19
A computer implemented method for pattern enhancement comprising:
- determining a range of process variations of a plurality of nominal process conditions for a lithographic process;
- determining a probability distribution of the range of process variations of the plurality of nominal process conditions during a predefined circuit manufacturing process using the determined range, wherein the probability distribution is determined through test pattern measurements from the predefined manufacturing process;
- defining a process domain, wherein the process domain defines limits of the range of process variations of the plurality of nominal process conditions and the limits are respectively based on determined probability distributions of the nominal process conditions;
- simulating a circuit feature of a circuit design layout within the limits of a defined process domain;
- and
- utilizing a computer to flag or correct the circuit design layout based on results from the simulation of the circuit feature.
3 more elements
A computer program product comprising a non-transitory computer useable medium having computer readable program code functions embedded in the medium for pattern enhancement comprising:
- computer readable program code that causes the computer to determine a range of process variations of a plurality of nominal process conditions for a lithographic process;
- computer readable program code that causes the computer to determine a probability distribution-of the range of process variations of the plurality of nominal process conditions during a predefined circuit manufacturing process using the determined range, wherein the probability distribution is determined through test pattern measurements from the predefined manufacturing process;
- computer readable program code that causes the computer to define a process domain, wherein the process domain is limits of the range of process variations of the plurality of nominal process conditions and the limits are respectively based on determined probability distributions of the nominal process conditions;
- computer readable program code that causes the computer to simulate a circuit feature of a circuit design layout within limits of a defined process domain;
- and
- computer readable program code that causes the computer to correct the circuit design layout based on results from the simulation of the circuit feature.
3 more elements
Dependencies are inferred from the claim text.