Analog-to-digital conversion in pixel arrays
AssigneeCmosis NV
InventorJan Bogaerts
Life of this patent
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Abstract
An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.
Claims20
An analog-to-digital converter for generating an output digital value equivalent to the difference between two analog signal values comprising:
- at least one input for receiving a first analog signal level and a second analog signal level;
- an input for receiving a ramp signal;
- a counter which is operable to count in a single direction;
- a control stage which is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal;
- and
- an output for outputting a value accumulated by the counter during a period when it is enabled, wherein
- the analog-to-digital converter is operable over a conversion cycle having two phases, with the ramp signal being reset between phases, and wherein the control stage is operable:
- during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the counter during a portion of the time period between the time at which the ramp signal equals the first analog signal level and an end of the ramp signal, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the second analog signal level;
- or,
- during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the first analog signal level, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the counter during a portion of the time period between the time at which the ramp signal equals the second analog signal level and an end of the ramp signal.
A method of generating an output digital value equivalent to the difference between two analog signal values during a conversion cycle, the method comprising:
- receiving a first analog signal level and a second analog signal level;
- receiving a ramp signal;
- enabling a counter, which is operable to count in a single direction, based on a comparison of the ramp signal with the first analog signal and the second analog signal by one of:
- during a first phase of the conversion cycle, comparing the ramp signal with the first analog signal level and enabling the counter during a portion of the time period between the time at which the ramp signal equals the first analog signal level and an end of the ramp signal, and during a second phase of the conversion cycle, comparing the ramp signal with the second analog signal level and enabling the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the second analog signal level;
- or,
- during a first phase of the conversion cycle, comparing the ramp signal with the first analog signal level and enabling the counter during a portion of the time period between a start of the ramp signal and a time at which the ramp signal equals the first analog signal level, and during a second phase of the conversion cycle, comparing the ramp signal with the second analog signal level and enabling the counter during a portion of the time period between the time at which the ramp signal equals the second analog signal level and an end of the ramp signal;
- and
- outputting a value accumulated by the counter during a period when it is enabled.
Dependencies are inferred from the claim text.