# US 7,877,874 B2 · Process for the collective fabrication of 3D electronic modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,877,874 B2 - Document ID: US7877874B2 - Status: Granted - Kind: B2 - Application number: 12/158,125 - Filed: 2006-12-19 - Published: 2008-11-27 - Granted: 2011-02-01 - Earliest claimed: 2005-12-23 - Assignees: 3D Plus - Inventors: Christian Val - Web page: https://patentgrep.com/patent/US7877874B2 ## CPC - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/801: {Interconnections on sidewalls of containers} - Y10T 29/49126: Assembling bases - Y10T 29/49146: with encapsulating, e.g., potting, etc. - Y10T 29/49165: by forming conductive walled aperture in base - Y10T 29/49169: Assembling electrical component directly to terminal or elongated conductor - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract The invention relates to the collective fabrication of n 3D modules. A batch of n wafers I are fabricated on one and the same plate. This step is repeated K times. The K plates are stacked. Plated-through holes are formed in the thickness of the stack. These holes are intended for connecting the slices together. The stack is cut in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2′ placed on said face. ## Claims ### Claim 1 A method of fabricating n electronic modules, n being an integer greater than 1, a module comprising a stack of K electronic wafers, a wafer i, i varying from 1 to K comprising on an insulating substrate at least one electronic component, the K wafers being electrically interlinked by conductors located on the lateral sides of the stack, wherein the fabrication is collective, comprising the steps of: a first step comprising, for each wafer i, in: A1) a step for fabricating a batch of n wafers i on one and the same flat thin sheet of thickness ep comprising silicon, covered on one face with a thin electrically insulating layer of thickness ei, forming the substrate, with, on this face, grooves of width L1 and of depth greater than ei and less than ep+ei, these grooves delimiting at least n geometrical patterns, each pattern being provided with at least one silicon electronic component connected to electrical connection terminals disposed on said face, the terminals being linked to electrical connection elements extending at least as far as a groove, a hole-opening area being provided at the intersection of the grooves and of the connection elements, the transverse dimension of this area being less than L1, the components being coated with an insulating resin which also fills the grooves, B1) a thinning step by surface grinding of the other face of the sheet so as to reveal the resin of the grooves, a second step comprising: A2) stacking and assembling the K batches obtained on completion of the first step, so as to superimpose the opening areas, substantially one on top of the other, B2) drilling holes in the resin perpendicularly to the faces of the sheets through the entire thickness of the stack plumb with the opening areas, the transverse dimension of the holes being less than L1, so that the silicon is insulated from the wall of the hole by the resin, C2) metallizing the wall of the holes, D2) cutting the stack along the grooves in order to obtain the n electronic modules. ### Claim 2 (depends on 1) The method as claimed in claim 1, comprising, prior to the second step, a step for thinning the sheet by surface grinding of the face of the sheet comprising the components. ### Claim 3 (depends on 2) The method as claimed in claim 2, wherein, prior to the step D2, it comprises a step consisting in depositing an electrically insulating layer on one face of the stack parallel to the sheets, this layer comprising, at the level of each pattern, elements for electrically interconnecting the module which provide opening areas centered on the opening areas of the wafers, and which extend as far as these areas. ### Claim 4 (depends on 2) The method as claimed in claim 2, wherein the second step also comprises a step following the step for metallizing the walls of the holes, consisting in refilling the holes with resin in order to facilitate the subsequent cutting of the stack. ### Claim 5 (depends on 2) The method as claimed in claim 2, wherein the electronic component is an active or passive component or an MEMS. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein, prior to the step D2, it comprises a step consisting in depositing an electrically insulating layer on one face of the stack parallel to the sheets, this layer comprising, at the level of each pattern, elements for electrically interconnecting the module which provide opening areas centered on the opening areas of the wafers, and which extend as far as these areas. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein the second step also comprises a step following the step for metallizing the walls of the holes, consisting in refilling the holes with resin in order to facilitate the subsequent cutting of the stack. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein the electronic component is an active or passive component or an MEMS. ### Claim 9 (depends on 8) The method as claimed in claim 8, wherein the active component is a bare chip. ### Claim 10 (depends on 8) The method as claimed in claim 8, wherein the electrical connection elements straddle the grooves. ### Claim 11 (depends on 10) The method as claimed in claim 10, wherein the electrical connection elements link two terminals located either side of a groove. ### Claim 12 (depends on 11) The method as claimed in claim 11, comprising, prior to the cutting of the step D2, a step of electrically testing the resulting stack. ### Claim 13 (depends on 1) The method as claimed in claim 1, wherein at least one passive component is located in or on the sheet. ### Claim 14 (depends on 1) The method as claimed in claim 1, wherein the insulating thin layer is made of insulating resin. ### Claim 15 (depends on 1) The method as claimed in claim 1, wherein the electrical connection elements are etched bridges. ### Claim 16 (depends on 15) The method as claimed in claim 15, wherein the bridges are etched after having filled the grooves with resin and before coating the components with resin. ### Claim 17 (depends on 16) The method as claimed in claim 16, wherein the holes are drilled by dry etching. ### Claim 18 (depends on 1) The method as claimed in claim 1, wherein the electrical connection elements are wired filaments. ### Claim 19 (depends on 18) The method as claimed in claim 18, wherein the filaments are cropped along the grooves. ### Claim 20 (depends on 18) The method as claimed in claim 18, wherein the holes are drilled by liquid etching.