Semiconductor storage device

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of bit lines intersecting with the plurality of word lines;
• a plurality of memory cells arranged at the intersections of the plurality of word lines and the plurality of bit lines and each including a transistor and a storage device whose resistance changes according to storage information;
• a plurality of hierarchy switches each arranged between the plurality of word lines at a constant interval;
• a common data line;
• a switch circuit arranged between the plurality of bit lines and the common data line and for selecting one of the plurality of bit lines to connect the one to the common data line;
• and
• a rewriting circuit connected to the common data line, wherein
• a first hierarchy switch of the plurality of hierarchy switches is inserted between a first bit line of the plurality of bit lines and a first memory cell of the plurality of memory cells and between a ground voltage terminal and the first memory cell, and a second hierarchy switch of the plurality of the hierarchy switches is inserted between the first bit line and a second memory cell of the plurality of memory cells and between the ground voltage terminal and the second memory cell.

A semiconductor storage device comprising:

• a first phase change thin film having two stable phases of a crystal state having a first resistance value and an amorphous state having a resistance value higher than the first resistance value;
• a first electrode provided on one side of the first phase change thin film;
• a second electrode provided on the other side of the first phase change thin film;
• a first transistor whose drain terminal is connected to the first electrode, whose source terminal is connected to the second electrode, and whose gate terminal is connected to a first word line;
• a second phase change thin film having two stable phases of the crystal state having the first resistance value and the amorphous state having the resistance value higher than the first resistance value;
• a third electrode connected to the second electrode and provided on one side of the second phase change thin film;
• a fourth electrode provided on the other side of the second phase change thin film;
• and
• a second transistor whose drain terminal is connected to the third electrode, whose source terminal is connected to the fourth electrode, and whose gate terminal is connected to a second word line, wherein
• a first memory cell is configured with the first transistor and a first phase change region in the phase change thin film sandwiched between the first electrode and the second electrode,
• a second memory cell is configured with the second transistor and a second phase change region in the phase change thin film sandwiched between the third electrode and the fourth electrode,
• at a writing operation of information to the first memory cell, the first transistor is turned off and the second transistor is turned on to carry a current from the first electrode to the fourth electrode, and
• at a writing operation of information to the second memory cell, the first transistor is turned on and the second transistor is turned off to carry a current from the first electrode to the fourth electrode.