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US 7,864,507 B2Granted
Capacitors with low equivalent series resistance
AssigneeTPL, Inc.
InventorsPatrick Franz Fleig, Charles D. E. Lakeman, Mark Fuge
Life of this patent
Estimating the term…
Abstract
An electric double layer capacitor (EDLC) in a coin or button cell configuration having low equivalent series resistance (ESR). The capacitor comprises mesh or other porous metal that is attached via conducting adhesive to one or both the current collectors. The mesh is embedded into the surface of the adjacent electrode, thereby reducing the interfacial resistance between the electrode and the current collector, thus reducing the ESR of the capacitor.
Claims10
A coin cell capacitor comprising:
- two current collectors configured to form a coin cell capacitor;
- a porous electrode;
- and
- a porous metal disc in electrical contact with one of said current collectors and at least partially embedded in a surface of said electrode;
- wherein during manufacture said electrode was sufficiently locally deformable to be imprinted by a surface pattern of said disc.
2 more elements
Dependencies are inferred from the claim text.