Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system

A board-mounted FLASH-based memory storage system comprising:

• a printed circuit board;
• a plurality of FLASH memory devices, each mounted to the printed circuit board;
• a controller mounted to the printed circuit board;
• and
• a plurality of communication buses, each configured to allow the controller to write a plurality of data collections to one or more FLASH memory devices wherein each such data collection is stored in a physical memory location;
• wherein the controller is configured to write data to the FLASH memory devices in a striped fashion using data stripes, where each data stripe includes a group of data collections and an associated set of data protection information such that
• (a) each data collection within a data stripe is written into a physical memory location in a FLASH memory device that differs from both (i) the FLASH memory devices into which the other data collections within the data stripe are written and (ii) the FLASH memory device to which the data protection information for the data stripe is written;
• (b) the communication bus used to write each data collection into a FLASH memory device differs from the communication buses used to write the other data collections within the data stripe into their respective FLASH memory devices;
• (c) the controller is configured to assemble data stripes using physical memory locations previously used to store data and to adjust the number of data collections within each assembled data stripe such that:
• (i) a physical memory location previously included in a data stripe having a given number of data collections is assembled into a data stripe having a different number of data collections and (ii) each of the FLASH memory devices includes physical memory locations having the capability of storing data associated with data stripes having different numbers of data collections.

A board-mounted FLASH-based solid state memory system comprising:

• a printed circuit board;
• a plurality of FLASH memory devices, each mounted to the printed circuit board, each FLASH memory device including a physical memory space divided into blocks, with each block being divided into a plurality of pages, with each block reflecting a grouping of memory locations that are erased at the same time and each page reflecting a memory location to which a number of bits of information is written, the physical memory space within each FLASH memory device being further divided into planes, with each plane being a group of blocks for which data is written from one page within the group to another page within the group without providing data external to the FLASH memory device;
• a controller mounted to the printed circuit board and having communication circuitry such that the controller is adapted to communicate independently and simultaneously over a plurality of communication channels;
• a plurality of communication buses, each communication bus forming a communication channel and coupling the controller to two or more FLASH memory devices, each channel allowing the controller to write bits of information to physical memory locations within the FLASH memory devices coupled to that channel,
• wherein the controller is configured to:
• (i) store information in the FLASH chips in the form of page stripes, each page stripe comprising a plurality of pages of data stored in the FLASH memory devices, each page within a given page stripe being stored in a FLASH memory device that is different from the FLASH memory device in which the other pages from that page stripe are stored;
• (ii) maintain a plurality of buffers containing information reflecting blocks of memory within the FLASH memory devices that have previously been used to store information and are available to be erased for the storage of different information, such buffers being maintained such that each block of memory is associated with a specific plane and a specific channel;
• (iii) dynamically assemble page stripes using the information contained in the plurality of buffers such that:
• a. the number of physical memory locations included in the page stripes varies from a first number to a second number, where the second number is smaller than the first number;
• b. each memory location within a page stripe having the second number of physical memory locations was previously included in a page stripe having the first number of physical memory locations;
• c. each of the memory locations within each page stripe is within a FLASH memory device accessible to the controller over a channel that is different from the channels used by the controller to access the FLASH memory devices within which the other memory locations within the stripe are found;
• and
• d. all of the physical memory locations within each page stripe are located within the same plane of the respective physical memory devices within which they are located.