MIM capacitor and metal gate transistor

A device comprising a capacitor and a transistor, comprising:

• a substrate comprising a mixed mode region adjacent to a logic circuit region;
• a bottom electrode, comprising a first metal, overlying a first insulator region in the mixed mode region;
• a first insulator layer overlying the mixed mode region, the logic circuit region, and the bottom electrode, wherein the first insulator layer comprises a first opening connecting parts of the bottom electrode, and a second opening and a third opening respectively connecting a semiconductor region and a second insulator region in the logic circuit region of the substrate;
• a dielectric film lining the first, second and third openings, disposed directly on the bottom electrode and sidewalls of the first, second and third openings, and overlying the semiconductor region and the second insulator region in the logic circuit region, respectively acting as a capacitor dielectric film and a gate dielectric in the mixed mode region and the logic circuit region;
• a second metal overlying the dielectric film, respectively acting as a top electrode of a capacitor structure in the mixed mode region in the first opening, a first metal gate electrode acting as a real gate electrode of a transistor structure in the logic circuit region in the second opening, and a second metal gate electrode in the third opening, wherein the dielectric film lines sidewalls of the top electrode and the first and second metal gate electrodes;
• and
• a second insulator layer overlying the capacitor structure and the transistor structure,
• wherein the second metal gate electrode and the top electrode substantially have the same thickness, and the first insulator region and the second region substantially have the same depth.

A device comprising a capacitor and a transistor comprising:

• a substrate comprising a semiconductor region between a first insulator region and a second insulator region;
• a bottom electrode, comprising a first conductor, disposed on the first insulator region;
• an insulator layer overlying the first and second insulator regions, the semiconductor region, and the bottom electrode, wherein the insulator layer comprises a first opening connecting parts of the bottom electrode, a second opening connecting the semiconductor region, and a third opening connecting the second insulator region;
• a dielectric film lining the first, second and third openings, and disposed on the bottom electrode and the semiconductor region and the second insulator regions, respectively acting as a capacitor dielectric film and a gate dielectric, wherein the dielectric film is disposed directly on sidewalls of the first, second and third openings;
• and
• a second conductor disposed on the capacitor dielectric film and the gate dielectric in the first, second and third openings, respectively acting as a top electrode of a capacitor structure, a first metal gate electrode acting as a real gate electrode of a transistor structure, and a second metal gate electrode in the third opening,
• wherein the second metal gate electrode and the top electrode substantially have the same thickness, and the first insulator region and the second region substantially have the same depth.