Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor

A mode control register within a multithreaded processor, the mode control register comprising:

• a first data field storing first data, wherein an execution mode of a first program thread of the multithreaded processor is selected according to the first data stored at the first data field and wherein the execution mode of the first program thread is a selectable one of a wait mode, a run mode, an off mode, and a debug mode;
• a second data field storing second data, wherein the second data is to determine an execution mode of a second program thread of the multithreaded processor;
• and
• logic coupled to the mode control register, wherein the logic is configured to modify the first data stored at the first data field by applying a mask to the mode control register.

A global control register comprising a mode control register, the mode control register comprising:

• a first field storing first data , wherein an execution mode of a first thread of a multiprocessor is a selectable one of a wait mode, a run mode, an off mode, and a debug mode and wherein the execution mode of the first thread is selected according the stored first data;
• a second field to determine an execution mode of a second thread of the multithreaded processor;
• and
• logic coupled to the mode control register, wherein the logic is configured to modify the first data stored at the first data field by applying a mask to the mode control register.

A method comprising:

• receiving a first control signal from a first thread;
• changing contents of a control register in response to the first control signal;
• and
• placing a second thread into a selectable one of at least an active mode, a wait mode, an off mode, and a debug mode,
• wherein the selection is based on the contents of the control register;
• wherein the control register includes a plurality of data fields;
• wherein the execution mode of the second thread is selected based on contents of a particular one of the plurality of data fields;
• and
• wherein the contents of the control register are changed by applying a mask to the control register, wherein applying the mask to the control register comprises changing the contents of the particular one of the plurality of data fields without changing contents of another of the plurality of data fields.

An apparatus comprising:

• a multithreaded processor;
• a control module to control a plurality of program threads, wherein each of the plurality of program threads is executable by the multithreaded processor;
• a thread mode module to receive a thread execution mode request from a first program thread of the plurality of program threads;
• a thread control register responsive to the thread mode module, wherein an execution mode of a second program thread of the plurality of program threads is a selectable one of a wait mode, a run mode, an off mode, and a debug mode, wherein a selection of the execution mode of the second program thread is based on contents of the thread control register;
• and
• a masking module to apply a mask to the thread control register, the mask to:
• enable a change of contents of a control field, the control field associated with the second program thread of the plurality of program threads;
• and
• leave contents of another control field unchanged, the another control field associated with a third program thread of the plurality of program threads.

A digital signal processor comprising:

• a multithreaded processor;
• and
• a global mode control register, the global mode control register including:
• a first field storing first data to determine an execution mode of a first thread of the multithreaded processor, wherein the execution mode of the first thread is selected to be one of a wait mode, a run mode, an off mode, and a debug mode according to the stored first data;
• a second field storing second data to determine an execution mode of a second thread of the multithreaded processor;
• and
• logic coupled to the global mode control register, wherein the logic is configured to modify the first data stored at the first data field by applying a mask to the global mode control register.

A portable communication device comprising:

• a digital signal processor, wherein the digital signal processor comprises:
• a memory;
• a register file coupled to the memory, the register file comprising a global mode control register, wherein the global mode control register includes:
• a first field storing first data to determine an execution mode of a first thread of the digital signal processor, wherein the execution mode of the first thread is a selectable one of an active mode, a wait mode, an off mode and a debug mode and wherein the execution mode of the first thread is determined according to the stored first data;
• and
• a second field storing second data to determine an execution mode of a second thread of the digital signal processor;
• and
• logic coupled to the global mode control register, wherein the logic is configured to modify the first data stored at the first data field by applying a mask to the global mode control register.

A processor comprising:

• means for processing a plurality of program threads;
• means for controlling an execution mode of each of the plurality of program threads, wherein:
• the execution mode of a first thread of the plurality of program threads is a selectable one of a wait mode, a run mode, an off mode, and a debug mode and wherein the execution mode of the first thread is determined according to first data stored at a mode control register;
• and
• the execution mode of a second thread of the plurality of program threads is a selectable one of the wait mode, the run mode, the off mode, and the debug mode, wherein the execution mode of the second thread is determined according to second data stored at the mode control register;
• and
• means for modifying the first data stored at the first data field by applying a mask to the global mode control register.