US 7,849,465 B2 · Programmable event driven yield mechanism which may activate service threads

Abstract

Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

Claims24

Dependent claims

An apparatus comprising:

hardware execution resources to execute at least one program;
a channel mechanism to hold a representation of a plurality of scenarios, wherein the channel mechanism is to associate a yield target address with each of the plurality of scenarios, and wherein each of the plurality of scenarios are based on a composite of more than one microarchitectural event;
and
a yield mechanism, in response to detecting a detected scenario of the plurality of scenarios, to selectively disrupt processing of the at least one program by transferring execution of the execution resources to code at the yield target address associated with the detected scenario by the channel mechanism;
and
wherein the yield target address is an address of a handler or service thread, and wherein the code at the yield target address associated with the detected scenario includes handler code or service thread code.

3 more elements

A system comprising:

a processor comprising
a plurality of hardware monitors to detect a plurality of architectural events;
one or more channel registers to specify a plurality of scenarios and a handler for each of the plurality of scenarios, wherein each of the plurality of scenarios include a combination of more than one of the plurality of architectural events to be detected by the plurality of hardware monitors;
and
event handler logic to invoke a handler specified for a detected scenario of the plurality scenarios in response to detecting the detected scenario;
and
a storage medium associated with the processor to store the handler specified for the detected scenario, the handler comprising at least one instruction, when executed, to cause a service thread to be generated;
and
wherein the one or more channel registers include a first amount of channel registers to specify a first number of scenarios of the plurality of scenarios and a handler for each of the first number of scenarios for a first privilege level and the one or more channel registers include a second amount of channel registers to specify a second number of scenarios for a second privilege level.

6 more elements

A processor comprising:

hardware execution resources to execute a plurality of instructions;
a first privilege level channel register, to be programmed by a first program at a first privilege level, to specify a first scenario associated with a first target address, wherein the first scenario includes a first combination of architectural events;
a second privilege level channel register, to be programmed by a second program that is at a second privilege level, to specify a second scenario associated with a second target address, wherein the second scenario includes a second combination of architectural events;
logic to cause a disruption of the first privilege level program and execution of code at the first target address in response to detecting the first scenario and to cause a disruption of the second level privilege program and execution of code at the second target address in response to detecting the second scenario;
wherein the first target address references an address of a first handler routine and the second target address references an address of a second handler routine, and wherein said disruption comprises calling the first handler or the second handler routine, accordingly;
wherein the first target address includes a first offset within a first code segment of the first privilege level program at which a first instruction of the first handler routine resides, and wherein the second target address includes a second offset within a second code segment of the second privilege level program at which a first instruction of the second handler routine resides.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/134,687Filed 19 May 2005 · continuation in part

Priority

19 Feb 2003

Published

US 2006/0294347 A128 Dec 2006

Granted

7 Dec 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/30
Using stored programs, i.e. using an internal store of processing equipment to receive or retain programs: arrangements for executing machine…
G06F 9/30087
To perform miscellaneous control operations, e.g. NOP: synchronisation or serialisation instructions
G06F 9/3009
To perform miscellaneous control operations, e.g. NOP: thread control instructions

Family

Application10/370,251Parent of this continuation-in-part · filed 19 Feb 2003

US 2006/0294347 A1Pre-grant publication · published 28 Dec 2006

US 7,487,502 B2Parent of this continuation-in-part

US 2004/0163083 A1Published application

US 7,849,465 B2This patent

From the US filing history. Foreign family members aren’t listed.

Programmable event driven yield mechanism which may activate service threads

Life of this patent

Programmable event driven yield mechanism which may activate service threads

Life of this patent

Abstract

Claims24