Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device

A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of:

• designating a plurality of primitive FlowModules;
• defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call;
• designating an Arc from a calling FlowGate to a called FlowGate
• generating a Signal for each named invocation of the called FlowGate, the designating the Arc and generating the Signal including,
• designating a TimedArc from the calling FlowGate to the called FlowGate;
• carrying a TimerSignal in a TimerChannel;
• and,
• delivering the TimerSignal in an order of time expiration relative to other TimerSignals, the designating including designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc;
• defining a Channel for carrying the Signal;
• and
• compiling the FlowModules for configuring one of the programmable hardware array or the programmable processor array.

A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of:

• designating a plurality of primitive FlowModules;
• defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interuptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call;
• designating an Arc from a calling FlowGate to a called FlowGate, the designating including,
• designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc;
• generating a Signal for each named invocation of the called FlowGate;
• defining a Channel for carrying the Signal;
• and
• compiling the FlowModules for configuring one of the programmable hardware array or the programmable processor array.