Reverse donut model

A method for generating a reverse donut model (RDM) for a block in an integrated circuit chip (IC) using a computer-aided design tool (CAD tool), comprising:

• obtaining connectivity information associated with a hierarchical model of the IC including connectivity information associated with a plurality of blocks, wherein each of the plurality of blocks includes one or more sub-blocks and one or more circuit elements with interconnections between the sub-blocks and circuit elements, each of the sub-blocks includes one or more circuit elements, each of the plurality of blocks includes an outer input-output (IO) pin layer with a plurality of input and output pins to interface with circuit elements both inside and outside the block, the connectivity information provided by a netlist;
• obtaining parasitic data associated with interconnections of the plurality of circuit elements and blocks of the IC, the parasitic data provided by a detailed standard parasitic format (DSPF) file;
• flattening the hierarchical model of the IC to a single level flat model using the information from the netlist and DSPF file, the single level flat model retaining all the blocks and circuit elements including connectivity and other related information of the IC;
• identifying a block from the plurality of blocks in the single level flat model of the IC, the identified block including logic associated with the plurality of input and output pins in the outer IO pin layer for interfacing with external circuit elements of the IC;
• initializing a timer associated with the IC;
• defining a plurality of timing constraints associated with each of the plurality of input and output pins of the IC;
• and
• generating the RDM of the identified block by retaining connectivity information associated with an outer boundary of the identified block and at least one layer of interface connection between each of the input and output pins of the identified block and at least one circuit element external to the identified block in the IC interfacing with each of the input and output pins in the outer boundary of the identified block,
• wherein the generating of the RDM includes pruning the single level flat model of the IC, the generated RDM preserving essential performance characteristics of the identified block and acting as a blackbox for the identified block, the generated RDM replacing the identified block in the IC for running the timing analysis and wherein the method operations are performed using a processor.

A pruning algorithm to generate a reverse donut model (RDM) for a block within an integrated circuit chip (IC), the pruning algorithm implemented in a simulation tool that is configured to execute on a computer system for performing analysis, the pruning algorithm comprising:

• (i) a flattener module configured to,
• flatten a hierarchical model of the IC to a single level flat model, the IC including a plurality of blocks, each of the plurality of blocks having one or more sub-blocks and one or more circuit elements arranged in a hierarchical structure, each of the sub-blocks including one or more circuit elements, wherein the single level flat model retaining all connectivity, parasitic data and other related information associated with each of the plurality of circuit elements and blocks within the IC;
• identify a block from the plurality of elements and blocks in the single level flat model;
• (ii) a timer module configured to,
• initialize timing constraints associated with the IC;
• define a plurality of timing constraints associated with each of a plurality of input and output pins of the identified block of the IC, the timing constraints providing timing data associated with the identified block;
• and
• (iii) a generator module configured to,
• interact with the flattener module to obtain list of circuit elements, blocks, connectivity and other related information for the identified block;
• interact with the timer module to obtain timing constraints associated with the identified block;
• prune the single level flat model of the IC to create the RDM for the identified block using the connectivity information and timing constraints associated with the identified block, the RDM including connectivity information of an outer input-output (IO) pin layer of the identified block and at least one layer of interface connection between each of a plurality of input and output pins in the IO pin layer of the identified block and a first external circuit element interfacing with each of the plurality of input and output pins, the RDM preserving essential performance characteristics of the identified block and acting as a blackbox for the identified block replacing the identified block during timing analysis,
• wherein the first external circuit element is a storage element, the storage element being one of a flip flop or a latch.