Efficient cell swapping system for leakage power reduction in a multi-threshold voltage process
AssigneeLSI Corporation
InventorBenjamin S. Sferrazza
Life of this patent
Estimating the term…
Abstract
A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The equivalent cells (i) decrease an overall delay of a path to meet a timing specification, and (ii) minimize an increase in overall leakage current.
Claims18
A method for designing an integrated circuit having a number of cells, comprising the steps of:
- (A) calculating a value using a computer for each of a plurality of equivalent cells in said design;
- and
- (B) selecting a number of said plurality of equivalent cells based on said values, wherein said equivalent cells (i) decrease an overall delay of a path to meet a timing specification, (ii) minimize an increase in overall leakage current, (iii) are configured to provide an operation equivalent to said cells and (iv) said values comprise a ratio of change in delay versus a change in leakage power.
A computer readable medium comprising computer executable instructions that, when executed by a computer, perform the steps of:
- (A) calculating an efficiency value using the computer for each of a plurality of equivalent cells in a design;
- and
- (B) selecting a number of said plurality of equivalent cells based on said values, wherein said equivalent cells (i) decrease an overall delay of a path to meet a timing specification, (ii) minimize an increase in overall leakage current, (iii) are configured to provide an operation equivalent to said cells and (iv) said efficiency values comprise a ratio of timing saved versus a increase in leakage power.
Dependencies are inferred from the claim text.