Back to results
US 7,849,387 B2Granted
Detecting architectural vulnerability of processor resources
AssigneeIntel Corporation
InventorsArijit Biswas, Niranjan Soundararajan, Shubhendu Mukherjee
Life of this patent
Estimating the term…
Abstract
In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
Claims22
An apparatus comprising:
- a plurality of counters to maintain utilization values, each for a storage unit of a processor during a quantum;
- a second counter to count a number of mispredictions made by a prediction unit of the processor during the quantum;
- and
- a first logic to determine a vulnerability measure for at least a first portion of the processor for the quantum based at least in part on the utilization values and the number of mispredictions.
1 more element
A method comprising:
- determining a quantized-architectural vulnerability factor (Q-AVF) value for a quantum for at least a portion of a processor using processor metric values, each corresponding to a utilization value for one of a plurality of front end structures of the processor;
- comparing the Q-AVF value to at least one threshold value;
- and
- dynamically controlling at least one error mitigation unit of the processor based on the comparison.
1 more element
A system comprising:
- a multicore processor having a plurality of cores, wherein a first core includes a detector to detect a vulnerability measure for the first core based on a plurality of processor metric values each associated with operation of a core structure during a first time period, and a controller to control an error mitigation unit of the first core based on the vulnerability measure, to enable an error detection mechanism of the error mitigation unit if the vulnerability measure is greater than a first threshold, and to enable an error correction mechanism of the error mitigation unit if the vulnerability measure is greater than a second threshold;
- and
- a dynamic random access memory (DRAM) coupled to the multicore processor.
Dependencies are inferred from the claim text.