Semiconductor test system
AssigneeYokogawa Electric Corporation
InventorsFumihiro Saito, Naoki Miyazaki
Life of this patent
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Abstract
A semiconductor test system includes: pin electronics (“PE”) cards each being operable to: a) apply a test pattern to device under tests (“DUTs”) each connected to the PE cards; b) capture patterns outputted in response to the test pattern from the DUTs; c) compare the patterns with an expected value pattern; and d) determine whether or not the patterns correspond with the expected value pattern, and a fail control card being operable to: e) aggregate fail information about the DUTs inputted through the PE cards every the DUTs; and f) transfer the fail information to the PE cards.
Claims5
A semiconductor test system comprising:
- pin electronics (“PE”) cards each being operable to:
- a) apply a test pattern to device under tests (“DUTs”) each connected to the PE cards;
- b) capture patterns outputted in response to the test pattern from the DUTs;
- c) compare the patterns with an expected value pattern;
- and
- d) determine whether or not the patterns correspond with the expected value pattern, and
- a fail control card being operable to:
- e) aggregate fail information about the DUTs inputted through the PE cards every the DUTs;
- and
- f) transfer the fail information to the PE cards.
A method of testing DUTs, the method comprising:
- i) applying a test pattern to the DUTs;
- ii) capturing patterns outputted in response to the test pattern from the DUTs;
- iii) aggregating fail information about the DUTs every the DUTs;
- iv) comparing the patterns with an expected value pattern using the aggregated fail information;
- and
- v) determining whether or not the patterns correspond with the expected value pattern.
Dependencies are inferred from the claim text.