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US 7,849,373 B2Granted
Method of testing a memory module and hub of the memory module
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
Life of this patent
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Abstract
Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
Claims10
A memory module, comprising:
- p memory chips;
- a hub to be converted into a control mode;
- a differential input circuit configured to receive differential pairs of packet signals through input terminals in a first mode in response to a mode control signal;
- a single ended input circuit configured to receive single ended input signals through the input terminals in a second mode in response to the mode control signal;
- a signal processing circuit configured to decode the differential pairs of packet signals outputted from the differential input circuit to control the p memory chips in the first mode;
- and
- a test circuit configured to test the p memory chips based on the single ended input signals received at the single ended input circuit, the test circuit includes:
- a first data path through which data are transferred between the signal processing circuit and the p memory chips in the first mode;
- a data writing circuit configured to allow test data provided from the single ended input circuit to be concurrently stored in the p memory chips in the second mode;
- and
- a comparison circuit configured to sequentially access the stored test data in the p memory chips, and configured to compare each of the accessed test data with expected data provided from the single-ended input circuit to generate a comparing result in the second mode, the comparison circuit includes:
- a multiplexer configured to access p×q bits of data of the p memory chips twice and to sequentially multiplex the accessed p×2×q bits of data in a unit of 2×q bits of data, the 2×q bits of data corresponding to the respective p memory chips;
- and
- a comparator configured to sequentially compare the multiplexed 2×q bits of data with 2×q bits of expected data provided from the single ended input circuit to generate the comparing result,
- wherein the differential input circuit and the single ended input circuit are disabled or enabled in response to the mode control signal.
12 more elements
A semiconductor chip module, comprising:
- a hub to be converted into a control mode;
- a pair of differential input terminals through which input signals are received;
- a differential input circuit configured to generate a differential signal in a first mode based on the input signals received by the pair of differential input terminals;
- a single-ended input circuit configured to produce two single ended signals in a second mode based on the input signals received from the pair of differential input terminals, and
- a comparison circuit configured to sequentially access a stored test data in p memory chips, and configured to compare each accessed test data with expected data provided from the single-ended input circuit to generate a comparing result in the second mode, the comparison circuit includes:
- a multiplexer configured to access p×q bits of data of the p memory chips twice and to sequentially multiplex the accessed p×2×q bits of data in a unit of 2×q bits of data, the 2×q bits of data corresponding to the respective p memory chips;
- and
- a comparator configured to sequentially compare the multiplexed 2×q bits of data with 2×q bits of expected data provided from the single ended input circuit to generate the comparing result,
- wherein the differential input signals and the single ended input signals are disabled or enabled in response to the control mode.
6 more elements
A memory module, comprising:
- p memory chips;
- a hub to be converted into a control mode;
- a differential input circuit configured to receive differential pairs of packet signals through input terminals in a first mode in response to a mode control signal;
- a single ended input circuit configured to receive single ended input signals through the input terminals in a second mode in response to the mode control signal;
- a signal processing circuit configured to decode the differential pairs of packet signals outputted from the differential input circuit to control the p memory chips in the first mode;
- a test circuit configured to test the p memory chips based on the single ended input signals received at the single ended input circuit, and
- a comparison circuit configured to sequentially access stored test data in the p memory chips, and configured to compare each accessed test data with expected data provided from the single-ended input circuit to generate a comparing result in the second mode, the comparison circuit includes:
- a multiplexer configured to access p×q bits of data of the p memory chips twice and to sequentially multiplex the accessed p×2×q bits of data in a unit of 2×q bits of data, the 2×q bits of data corresponding to the respective p memory chips;
- and
- a comparator configured to sequentially compare the multiplexed 2×q bits of data with 2×q bits of expected data provided from the single ended input circuit to generate the comparing result,
- wherein the differential input circuit and the single ended input circuit are disabled or enabled in response to the mode control signal.
8 more elements
Dependencies are inferred from the claim text.