Jitter producing circuitry and methods
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorsDavid Moshe, Erez Reches, Ido Naishtein
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Abstract
To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).
Claims21
A method facilitating testing of jitter tolerance of a serializer/deserializer (SERDES) subcircuit of an integrated circuit device comprising:
- deriving a periodic signal from a reference clock signal;
- counting cycles of the periodic signal so that a count of the cycles alternately increments and decrements between upper and lower limits;
- delaying the reference clock signal by an amount that is responsive to the count to produce a clock signal having cyclically varying jitter;
- selectively applying the clock signal having cyclically varying jitter to a first SERDES subcircuit of the device to cause the first SERDES subcircuit to output a serial data signal having cyclically varying jitter;
- and
- selectively applying the serial data signal output by the first SERDES subcircuit to a second SERDES subcircuit of the device.
An integrated circuit device for facilitating testing of jitter tolerance of serializer/deserializer (SERDES) means of the device comprising:
- means for deriving a periodic signal from a reference clock signal;
- means for counting cycles of the periodic signal so that a count of the cycles alternately increments and decrements between upper and lower limits;
- means for delaying the reference clock signal by an amount that is responsive to the count to produce a clock signal having cyclically varying jitter;
- first and second SERDES means for performing SERDES functions;
- means for selectively applying the clock signal having cyclically varying jitter to the first SERDES means to cause the first SERDES means to output a serial data signal having cyclically varying jitter;
- and
- means for applying a serial data input signal, which can be derived from the serial data signal output by the first SERDES means, to the second SERDES means.
An integrated circuit device for facilitating testing of jitter tolerance of a serializer/deserializer (SERDES) subcircuit of the device comprising:
- processing circuitry that derives a periodic signal from a reference clock signal;
- counter circuitry that counts cycles of the periodic signal so that a count of the cycles alternately increments and decrements between upper and lower limits;
- delay circuitry that delays the reference clock signal by an amount that is responsive to the count to produce a clock signal having cyclically varying jitter;
- first and second SERDES subcircuits;
- clock signal circuitry that selectively applies the clock signal having cyclically varying jitter to the first SERDES subcircuit to cause the first SERDES subcircuit to output a serial data signal having cyclically varying jitter;
- and
- input circuitry that applies a serial data input signal, which can be derived from the serial data signal output by the first SERDES subcircuit, to the second SERDES subcircuit.
Dependencies are inferred from the claim text.