Method and system for error correction in flash memory
AssigneeMarvell World Trade Ltd.
InventorsAditya Ramamoorthy, Zining Wu, Pantas Sutardja
Life of this patent
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Abstract
A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
Claims18
A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:
- an encoder adapted to receive a series of data bits and provide a series of encoded data bits;
- a mapper adapted to convert the series of encoded data bits into a series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;
- and
- a demodulator adapted to generate an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell;
- and
- a decoder adapted to output a series of output data symbols based on the output signal of the demodulator.
A method of operating a controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the method comprising:
- encoding a first series of data bits to provide a series of encoded data bits;
- converting the series of encoded data bits into a series of data symbols;
- storing the series of data symbols in a memory cell of the multi-level solid state non-volatile memory array;
- generating an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell;
- and
- decoding the output signal to provide a series of output data symbols.
A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:
- means for encoding a first series of data bits to provide a series of encoded data bits;
- means for converting the series of encoded data bits into a series of data symbols;
- means for storing the series of data symbols in a memory cell of the multi-level solid state non-volatile memory array;
- means for generating an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell;
- and
- means for decoding the output signal to provide a series of output data symbols.
Dependencies are inferred from the claim text.