US 7,843,907 B1Granted

Storage gateway target for fabric-backplane enterprise servers

AssigneeHabanero Holdings, Inc.

InventorsAkram A. Abou-Emara, Harinder Singh Bhasin, Sriram Chidambaram, Nakul Pratap Saraiya, Jia-Jen Yeh, Christopher Dean Youngworth

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Abstract

Storage gateway remote and local access to storage devices is provided in part via a target implementing bandwidth-controlled access to the devices. The target may be iSCSI-compatible, and may also optionally implement protection, security, and performance features. The protection and security features include any combination of VLANs, zoning, Logical Unit Number (LUN) masking, and encryption. The performance features include any combination of HW-accelerated Remote Direct Memory Access (RDMA), prioritized I/O operations, and service priority (such as strict priority and straight or weighted round-robin priorities). An initiator may be implemented in a Processor Memory Module (PMM) coupled to a switch fabric that is in turn coupled to a target implemented in a Fibre Channel Module (FCM). Storage traffic may be communicated as Small Computer System Interface (SCSI)- and SCSI over Transmission Control Protocol/Internet Protocol (iSCSI)-compatible information (data and commands) on the switch fabric via cellifying input/output interface devices.

Claims20

Dependent claims

A method comprising:

in one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor, initiating a mass storage session with a selected mass storage interface, the selected mass storage interface being coupled to the physical partitions via a switch fabric, the mass storage session at least in part via a mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;
accessing storage data via the selected mass storage interface in response to requests from the one of the physical partitions, the storage data being communicated in part via the switch fabric;
and
wherein the selected mass storage interface comprises a mass storage input/output controller, each physical partition comprises at least one respective partition input/output controller, each physical partition is formed at least in part by programmatically configuring links between processors of the physically partitionable symmetric multiprocessor to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis, and each of the input/output controllers is associated with one of a plurality of physical ports of the switch fabric and enabled to provide cellifying transport via the switch fabric at least in part by addressing cells to a particular one of the physical ports.

1 more element

A system comprising:

a switch fabric having a plurality of physical ports;
a mass storage interfacing element coupled to the switch fabric via a mass storage input/output controller;
a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition coupled to the switch fabric via at least one respective partition input/output controller, each physical partition comprising links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis;
wherein the mass storage interfacing element is enabled to execute a mass storage control process to control mass storage traffic, the mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;
and
wherein each of the input/output controllers is associated with a unique one of the physical ports of the switch fabric, and the input/output controllers are enabled to communicate the mass storage traffic between a plurality of processes executing on the physical partitions and the mass storage input/output controller at least in part by addressing cells to a particular one of the physical ports.

3 more elements

A non-transitory computer readable medium having a set of instructions stored therein which when executed by a computer causes the computer to perform functions comprising:

providing software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces;
providing initial mass storage system control information to one of a plurality of physical partitions of a physically partitionable symmetric multiprocessor via a switch fabric;
configuring a mass storage interface in accordance with the initial mass storage system control information, comprising receiving the initial mass storage system control information from the switch fabric;
accessing final mass storage system control information via the mass storage interface after the configuring of the mass storage interface;
reconfiguring the mass storage interface in accordance with the final mass storage system control information, comprising receiving the final mass storage system control information from the switch fabric;
wherein each physical partition is formed at least in part by programmatically configuring links between processors of the physically partitionable symmetric multiprocessor to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache coherency transactions on a link-by-link basis;
and
wherein the computer is included in the mass storage interface.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/256,688Filed 22 Oct 2005 · continuation in part
Priority: 13 Feb 2004
Granted: 30 Nov 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H04L 49/3045
Peripheral units, e.g. input or output ports: virtual queuing
H04L 47/6205
Characterised by scheduling criteria: arrangements for avoiding head of line blocking
H04L 49/90
Packet switching elements: buffering arrangements
H04L 49/901
Buffering arrangements: using storage descriptor, e.g. read or write pointers

Family

Application60/544,916Us provisional application · filed 13 Feb 2004
Application60/563,222Us provisional application · filed 17 Apr 2004
Application10/889,468Parent of this continuation-in-part · filed 12 Jul 2004
Application10/889,467Parent of this continuation-in-part · filed 12 Jul 2004
Application10/889,469Parent of this continuation-in-part · filed 12 Jul 2004
Application60/603,250Us provisional application · filed 20 Aug 2004
Application60/650,707Us provisional application · filed 7 Feb 2005
Application60/651,026Us provisional application · filed 7 Feb 2005
Application60/651,027Us provisional application · filed 7 Feb 2005
Application11/057,120Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,048Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,117Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,034Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,114Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,046Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,112Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,119Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,036Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,037Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,121Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,038Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,113Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,116Parent of this continuation-in-part · filed 12 Feb 2005
Application11/057,035Parent of this continuation-in-part · filed 15 Feb 2005
Application60/684,542Us provisional application · filed 25 May 2005
Application60/717,147Us provisional application · filed 14 Sep 2005
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US 7,664,110 B1Parent of this continuation-in-part
US 7,561,571 B1Parent of this continuation-in-part
US 7,757,033 B1Parent of this continuation-in-part
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From the US filing history. Foreign family members aren’t listed.