Method to reduce error in time interleaved analog-to-digital converters arising due to aperture delay mismatch
AssigneeAnalog Devices, Inc.
InventorGary Carreau
Life of this patent
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Abstract
A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.
Claims20
A control system for a time interleaved analog to digital converter (ADC) system comprising:
- a plurality of selection switch stages, one corresponding to each ADC in the system and coupled to a respective sampling capacitor thereof;
- a second switch stage coupled to a voltage source;
- a plurality of conductors extending between the second switch stage and each of the selection switch stages,
- wherein for each of N ADCs in the system, the selection switch stages and the second switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source.
An analog to digital converter (ADC) system comprising:
- N ADCs for time interleaved analog to digital conversion of an input signal,
- N selection switch stages, one corresponding to each ADC in the system and coupled to a respective sampling capacitor thereof;
- a second switch stage coupled to a voltage source;
- at least N+1 conductors extending between the second switch stage and each of the selection switch stages.
An aperture mismatch control method in time-interleaved integrated circuit system, comprising:
- sampling an input voltage on a time-interleaved basis at a plurality of sampling capacitors,
- while each respective capacitor is sampling the input voltage at a first plate thereof, connecting a second plate of the respective capacitor to a reference potential,
- wherein the connecting occurs through a randomly-selected one of a plurality of electrical paths between the second plate and the reference potential.
Dependencies are inferred from the claim text.