Programmable settling for high speed analog to digital converter
AssigneeBroadcom Corporation
InventorChun-Ying Chen
Life of this patent
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Abstract
In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.
Claims20
A method for varying a calibration signal bandwidth in an analog-to-digital converter, comprising:
- identifying a calibration mode;
- and
- during the calibration mode, adjusting a bandwidth-adjustable filter to process the calibration signal at a first bandwidth that is greater than a second bandwidth, wherein the second bandwidth is associated with an analog-to-digital conversion mode.
An apparatus for varying a calibration signal bandwidth in an analog-to-digital converter, comprising:
- means for identifying a calibration mode;
- and
- a bandwidth-adjustable filter coupled to the means for identifying and configured to process a calibration signal at a first bandwidth that is greater than a second bandwidth during the calibration mode, wherein the second bandwidth is associated with an analog-to-digital conversion mode.
A method for varying a calibration signal bandwidth in an analog-to-digital converter, comprising:
- adjusting a bandwidth-adjustable filter during the calibration mode to process the calibration signal at a first bandwidth that is greater than a second bandwidth, wherein the second bandwidth is associated with an analog-to-digital conversion mode;
- and
- varying the bandwidth-adjustable filter during the analog-to-digital conversion mode to process the calibration signal at the second bandwidth.
Dependencies are inferred from the claim text.