Programmable settling for high speed analog to digital converter
AssigneeBroadcom Corporation
InventorChun-Ying Chen
Life of this patent
Estimating the term…
Abstract
In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.
Claims14
An analog to digital converter (ADC), comprising:
- a reference voltage supply having an output;
- and
- an isolation transistor series-coupled with a filter capacitor between said reference voltage supply output and ground,
- wherein said isolation transistor isolates said filter capacitor during calibration of the ADC.
A method for reducing a calibration settling time in an analog-to-digital converter (ADC) having a filter capacitor, wherein the filter capacitor and an isolation transistor are coupled in series between a reference voltage supply output and ground, comprising:
- identifying a calibration mode of the ADC;
- and
- isolating the filter capacitor with the isolation transistor during said calibration mode.
A method for varying a calibration signal bandwidth in an analog-to-digital converter (ADC), wherein said calibration signal is passed through a bandwidth-adjustable filter, comprising:
- identifying a calibration mode of the ADC;
- and
- increasing a bandwidth of said bandwidth-adjustable filter during said calibration mode to vary the calibration signal bandwidth in the ADC.
Dependencies are inferred from the claim text.