Frequency synthesizer circuitry employing delay line
AssigneeAltera Corporation
InventorsTad Kwasniewski, Jingcheng Zhuang, Qingjin Du
Life of this patent
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Abstract
Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.
Claims14
Frequency synthesizer circuitry comprising:
- delay line circuitry having a plurality of successive stages through which a reference clock signal successively propagates, each of the stages including an output buffer that draws an amount of current indicative of a state of the reference clock signal currently in that stage;
- circuitry for adding the currents drawn by the output buffers and for producing an intermediate signal indicative of a result of the adding;
- and
- further output buffer ring oscillator circuitry for using fluctuations in the intermediate signal to produce a final output signal having frequency responsive to the fluctuations, wherein the further output buffer ring oscillator circuitry comprises:
- an AC coupling capacitor for passing an AC component of the intermediate signal;
- a plurality of inverters through which the AC component is passed in series;
- and
- a feedback connection including a resistor from an output of a last of the plurality of inverters to an input of a first of the plurality of inverters.
Frequency synthesizer circuitry comprising:
- delay line circuitry having a plurality of successive stages through which a reference clock signal successively propagates, each of the stages including an output buffer that draws an amount of current indicative of a state of the reference clock signal currently in that stage;
- a common node for adding the currents drawn by the output buffers;
- a resistor and a transistor connected in series between a power supply and the common node and a further node between the resistor and the transistor for producing an intermediate signal indicative of a result of the adding;
- and
- further output buffer ring oscillator circuitry for using fluctuations in the intermediate signal to produce a final output signal having frequency responsive to the fluctuations.
A method of synthesizing a frequency from a reference clock signal comprising:
- passing the reference clock signal through successive stages of a delay line;
- adding currents drawn by output buffers of the stages to produce an intermediate signal;
- and
- using fluctuations in the intermediate signal to produce a final output signal having a frequency that is based, at least in part, on frequency of the fluctuations, wherein the using comprises:
- extracting an AC component from the intermediate signal;
- passing the AC component through a plurality of inverters;
- and
- feeding back an output signal of a last of the plurality of inverters through a resistor to an input of a first of the plurality of inverters.
Frequency synthesizer circuitry comprising:
- a plurality of delay line stages connected in a series, each stage delaying and inverting a reference clock signal it receives from a preceding stage in the series, and each stage having an output buffer;
- a common node for adding current drawn by the output buffers;
- a voltage divider circuit for converting current at the common node to voltage of an intermediate signal, wherein the voltage divider circuit comprises a resistor connected in series with a transistor;
- and
- further output buffer ring oscillator circuitry for converting an AC component of the intermediate signal to a final output signal having a synthesized frequency.
A method of synthesizing a frequency from a reference clock signal comprising:
- passing the reference clock signal through successive stages of a delay line;
- adding currents drawn by output buffers of the stages to produce an intermediate signal;
- providing the intermediate signal using a voltage divider comprising a resistor and a transistor connected in series;
- and
- using fluctuations in the intermediate signal to produce a final output signal having a frequency that is based, at least in part, on frequency of the fluctuations.
Dependencies are inferred from the claim text.