Phase lock loop apparatus

A phase lock loop (PLL) apparatus, comprising:

• a plurality of phase detecting modules, when the plurality of phase detecting modules receive an input data signal and a clock signal, the plurality of phase detecting modules detecting the phase difference between input data signal and the clock signal to generate a plurality of first index signals;
• a logic processing module, coupled to the plurality of phase detecting modules, for receiving the plurality of first index signals and processing a high-frequency dithering to the plurality of first index signals to generate a second index signal;
• a charge pump and loop filter (CPLF), coupled to the logic processing module, for receiving the plurality of first index signals and the second index signal, adjusting a control voltage according to the plurality of first index signals and the second index signal, and then outputting the control voltage;
• and
• a voltage control oscillator, coupled to the CPLF, for adjusting frequency or phase of the clock signal according to the control voltage, and then outputting the adjusted clock signal to the plurality of phase detecting modules;
• wherein the frequency of outputting the second index signal is equal to or larger than the frequency of outputting one of the first index signals.