Methods and apparatus to reduce idle current in power amplifiers
AssigneeTexas Instruments Incorporated
InventorDaniel Andrew Mavencamp
Life of this patent
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Abstract
Power amplifiers with reduced idle currents are described. In some examples, a power amplifier includes a driver configured to generate a control signal based on an input signal. The power amplifier also includes a first output transistor configured to selectively provide an output signal via an output channel that has a resistance based on the control signal, and a channel adjuster configured to generate several digital signals based on the control signal. A composite switch, which includes several segment transistors, is included to selectively increase or decrease the output channel resistance based on the digital signals.
Claims20
A power amplifier circuit comprising:
- a driver configured to generate a control signal based on an input signal;
- a first output transistor coupled to the control signal, configured to selectively provide an output signal representative of the input signal, via an output channel having a resistance based on the control signal;
- a channel adjuster coupled to the control signal, configured to generate a plurality of digital signals based on the control signal;
- and
- a composite switch, comprising a plurality of segment transistors, configured to selectively increase or decrease the output channel resistance based on the plurality of digital signals to provide the output signal.
A method to reduce idle current in an amplifier, comprising:
- monitoring a first control signal to a first output transistor that provides a first output channel between a power supply and an output terminal;
- determining whether the first control signal has increased above a high threshold or decreased below a low threshold;
- decreasing the resistance of the first output channel in response to the first control signal increasing above the high threshold by enabling at least one of a plurality segment transistors to provide at least one parallel current path between the power supply and the output terminal so as to increase a channel width of the first output channel;
- and
- increasing the resistance of the first output channel in response to the first control signal decreasing below the low threshold by disabling at least one of the first segment transistor or a second segment transistor.
An apparatus comprising:
- a driver that receives an input signal and that generates a first control signal and a second control signal;
- a first field effect transistor (FET) that is coupled to the driver at its gate so as to receive the first control signal;
- a second FET that is coupled to the driver at its gate so as to receive the second control signal;
- a first channel adjuster is coupled to the driver;
- a second channel adjuster is coupled to the driver;
- a first set of segment transistors that are each coupled in parallel to the first FET and that are each coupled to the first channel adjuster, wherein the first channel adjuster selectively activates and deactivates segment transistors from the first set of segment transistors based at least in part on comparison between the first control signal and a plurality of thresholds;
- and
- a second set of segment transistors that are each coupled in parallel to the second FET and that are each coupled to the second channel adjuster, wherein the second channel adjuster selectively activates and deactivates segment transistors from the second set of segment transistors based at least in part on comparison between the second control signal and the plurality of thresholds.
Dependencies are inferred from the claim text.