Low latency synchronizer circuit
AssigneeApple Inc.
InventorsBo Tang, Edgardo F. Klass
Life of this patent
Estimating the term…
Abstract
A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.
Claims20
A synchronizer circuit comprising:
- a master stage including:
- a first master latch having a first data input coupled to receive a data input signal, and a first clock input coupled to receive a clock signal;
- a second master latch having a second data input coupled to receive the data input signal, and a second clock input coupled to receive a delayed version of the clock signal;
- and
- a pull-up circuit configured to drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch;
- and
- a slave stage including a slave latch having an input coupled to the output line of the master stage.
An integrated circuit comprising:
- a circuit;
- and
- a synchronizer circuit coupled to the circuit and configured to receive an input data signal and to provide to the circuit an output data signal that corresponds to the input data signal in response to receiving a clock signal, wherein the synchronizer circuit includes:
- a master stage including:
- a first master latch having a first data input coupled to receive the input data signal, and a first clock input coupled to receive the clock signal;
- a second master latch having a second data input coupled to receive the input data signal, and a second clock input coupled to receive a delayed version of the clock signal;
- and
- a pull-up circuit configured to drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch;
- and
- a slave stage including a slave latch having an input coupled to the output line of the master stage, wherein the slave stage is configured to provide the output data signal.
A synchronizer circuit comprising:
- a master stage including:
- a plurality of master latches, each having an input coupled to receive an input data signal;
- wherein a first latch is coupled to receive a clock signal, and each other remaining latches is coupled to receive a delayed version of the clock signal, wherein each delayed version of the clock signal has a different delay;
- a pull-up circuit configured to drive an output line of the master stage depending upon an output of each latch of the plurality of master latches;
- and
- a slave stage including a slave latch having an input coupled to the output line of the master stage.
A system comprising:
- a first circuit configured to provide a data signal according to a first clock signal;
- and
- a second circuit including a synchronizer circuit configured to receive and sample the data signal according to a second clock signal;
- wherein the synchronizer circuit includes:
- a master stage including:
- a plurality of master latches, each having an input coupled to receive the data signal;
- wherein a first latch is coupled to receive the second clock signal, and each other remaining latches is coupled to receive a delayed version of the second clock signal, wherein each delayed version of the second clock signal has a different delay;
- a pull-up circuit configured to drive an output line of the master stage depending upon an output of each latch of the plurality of master latches;
- and
- a slave stage including a slave latch having an input coupled to the output line of the master stage.
Dependencies are inferred from the claim text.