Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit

A pipeline circuit comprising:

• a pulse generating circuit configured to generate a delayed signal of a clock signal and an inversion signal of a pulse signal;
• a first flip-flop group including a plurality of flip-flops, the first flip-flop group configured to generate output signals by sampling input signals in response to the delayed signal of the clock signal and the inversion signal of the pulse signal;
• a combination logic circuit configured to perform a logic operation on the output signals received from the first flip-flop group;
• and
• a second flip-flop group including a plurality of flip-flops, the second flip-flop group configured to generate output signals by sampling signals received from the combination logic circuit in response to the delayed signal of the clock signal and the inversion signal of the pulse signal,
• wherein each of the flip-flops included in the first and second flip-flop groups includes:
• a precharge transistor configured to precharge an internal node to a first power supply voltage in response to the clock signal;
• a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, the second power supply voltage being lower than the first power supply voltage;
• a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node;
• and
• a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage, wherein the first pull-down unit includes:
• a first pull-down transistor configured to pull down the voltage of the internal node in response to an input data signal, the input data signal being one of the sampled input signals;
• and
• a second pull-down transistor configured to pull down the voltage being pulled down by the first pull-down transistor to the second power supply voltage in response to a first pulse signal, and to not pull down the voltage being pulled down by the first pull-down transistor in response to the output signal.

A pipeline circuit comprising:

• a pulse generating circuit configured to generate a delayed signal of a clock signal and an inversion signal of a pulse signal;
• a plurality of flip-flop groups, each flip-flop group including a plurality of flip-flops and configured to generate output signals by sampling input signals in response to the delayed signal of the clock signal and the inversion signal of the pulse signal;
• and
• a plurality of combination logic circuits connected between the plurality of flip-flop groups, wherein each combination logic circuit is configured perform a logic operation on the output signals received from a corresponding flip-flop group among the plurality of flip-flop groups to generate output signals, and to apply the output signals to a subsequent flip-flop group,
• wherein each of the flip-flops includes:
• a precharge transistor configured to precharge an internal node to a first power supply voltage in response to the clock signal;
• a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, the second power supply voltage being lower than the first power supply voltage;
• a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node;
• and
• a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage, wherein the first pull-down unit includes:
• a first pull-down transistor configured to pull down the voltage of the internal node in response to an input data signal, the input data signal being one of the sampled input signals;
• and
• a second pull-down transistor configured to pull down the voltage being pulled down by the first pull-down transistor to the second power supply voltage in response to a first pulse signal, and to not pull down the voltage being pulled down by the first pull-down transistor in response to the output signal.

A method of operating a flip-flop circuit, the method comprising:

• precharging an internal node to a first power supply voltage in response to a clock signal;
• pulling down a voltage of the internal node by using a first pull-down transistor in response to an input data signal;
• pulling down the voltage being pulled down by the first pull-down transistor to a second power supply voltage by using a second pull-down transistor in response to a pulse signal, and not pulling down the voltage being pulled down by the first pull-down transistor by using the second pull-down transistor in response to an output signal,
• the pulse signal being generated from a combination of the clock signal and the output signal, the second power supply voltage being lower than the first power supply voltage;
• and
• pulling up a voltage of an output node to the first power supply voltage in response to the voltage being pulled down by the second pull-down transistor.