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US 7,843,240 B2Granted
Delay locked loop circuit
AssigneeHynix Semiconductor Inc.
InventorTae-Kyun Kim
Life of this patent
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Abstract
A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.
Claims10
A delay locked loop circuit, comprising:
- a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock generated by delaying an external clock for a second delay amount with a phase of a feedback clock generated in response to delay modeling of a semiconductor memory device;
- and
- a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than the second delay amount after locking the internal clock,
- wherein the noise sensor includes:
- a first phase comparator configured to generate a first phase comparison signal that is enabled when phases of the external clock and the feedback clock are inverted;
- and
- a monitoring unit configured to disable variation of the first delay amount when the first phase comparison signal is enabled.
4 more elements
A delay locked loop circuit comprising:
- a phase comparator configured to generate a first comparison signal by detecting a phase difference of a reference clock and a second feedback clock;
- a delay controller configured to decide a first delay amount in response to the first phase comparison signal;
- a first delay unit configured to output an internal clock by delaying the reference clock as much as the first delay amount;
- a replica model unit configured to receive the internal clock and output a first feedback clock;
- a second delay unit configured to output the reference clock by delaying an external clock of a semiconductor memory device as much as a second delay amount;
- a third delay unit configured to output the second feedback clock by delaying the first feedback clock as much as the second delay amount;
- and
- a noise controller configured to control variation of the first delay amount by sensing whether the first delay amount varies due to an external noise or not when the internal clock is locked.
5 more elements
Dependencies are inferred from the claim text.