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US 7,843,236 B2Granted
Low voltage differential signal receiver
AssigneeEtron Technology, Inc.
InventorsChen-Yuan Chang, Hsien-Sheng Huang
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Abstract
The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.
Claims14
A low voltage differential signal receiver comprising:
- an input stage circuit converting a low voltage differential signal into a first current signal and a second current signal, wherein said low voltage differential signal comprises a first input voltage signal and a second input voltage signal;
- a current source circuit coupled to said input stage circuit and generating a set of operating currents required by said input stage circuit according to a plurality of bias signals;
- a current mirror circuit coupled to said current source circuit and said input stage circuit, receiving said first current signal and said second current signal to generate an output voltage signal, and generating said bias signals to said current source circuit according to said first current signal and said second current signal, and
- a fail-safe circuit coupled to said current mirror circuit, wherein
- when an absolute value of difference of said first input voltage signal and said second input voltage signal is greater than a predetermined value, said fail-safe circuit switches said output voltage signal from an original first predetermined voltage value to a second predetermined voltage value;
- and
- when the absolute value of difference of said first input voltage signal and said second input voltage signal is less than said predetermined value, said fail-safe circuit maintains said output voltage signal at said first predetermined voltage value.
4 more elements
Dependencies are inferred from the claim text.