Break-before-make predriver and level-shifter

A driver circuit, comprising:

• an input inverter configured to receive an input signal;
• two cross-coupled inverters that include a first and second NFET and a first and second PFET, wherein the first NFET is configured to receive the output of the input inverter, and wherein the second NFET is configured to receive the input signal;
• first and second output buffers configured to receive first and second outputs of the two cross-coupled inverters, wherein said first buffer inverts said first output and said second buffer leaves said second output uninverted;
• wherein the NFETs of the cross-coupled inverters are larger than the PFETs of the cross-coupled inverters, said NFETs and PFETs being sized with respect to each other such that:
• each of the first and second outputs of the two cross-coupled inverters falls to logic zero before the other of the first and second outputs rises to logic one in response to a transition in the input signal so that:
• a first break before make delay is created between a first predriver output signal at a first predriver output node and a second predriver output signal at a second predriver output node;
• and
• a second break before make delay is created between the second predriver output signal at the second predriver output node and the first predriver output signal at the first predriver output node;
• and
• first and second tristate devices configured to disable output signals of the first and second predriver output nodes.

A break-before-make predriver, comprising:

• inverter means for receiving an input signal and inverting said input signal;
• cross-coupled inverter means for providing a break-before-make delay, wherein the cross-coupled inverter means is configured to receive the output of the inverter means, the cross-coupled inverter means is further configured to receive the input signal, the cross-coupled inverter means includes first and second outputs, the first output has a first delay charging relative to the second output discharging, the second output has a second delay charging relative to the first output discharging, and said first and second delays are created by the unequal transistor sizes of the cross-coupled inverters;
• first and second output buffer means for receiving the first and second outputs of the cross-coupled inverter means, for inverting the first output of the cross-coupled inverter means while leaving the second output of the cross-coupled inverter means uninverted so that the first output buffer means provides a break transition before the second output buffer means provides a make transition due to the second delay, and the second output buffer means provides a break transition before the first output buffer means provides a make transition due to the first delay;
• and
• first and second tristate means for disabling output signals of the first and second predriver output nodes.

In a circuit having an input inverter configured to receive an input signal, two cross-coupled inverters including a pair of NFETs and a pair of PFETs, and first and second output buffers, a sizing method for creating a break before make delay with substantially equal action on rising and falling edges, the method comprising:

• sizing the NFETs and PFETs of the cross-coupled inverters such that each of the NFETs are larger than each of the PFETs of the cross-coupled inverters so that a first time constant to charge a first output of the cross-coupled inverters is greater than a second time constant to discharge a second output so that the second output discharges before the first output charges;
• and so that a third time constant to charge the second output of the cross-coupled inverters is greater than a fourth time constant to discharge the first output so that the first output discharges before the second output charges;
• sizing the input inverter, the cross-coupled inverters and the first and second output buffers with respect to each other such that first and second delays between an input signal and predriver make signals on a rising and falling edge, respectively, are substantially equal;
• sizing the input inverter, the cross-coupled inverters and the first and second output buffers with respect to each other such that a third and fourth delays between a break signal and make signal on a rising edge and falling edge, respectively, are substantially equal;
• configuring the first and second output buffers such that the break signal on the rising edge occurs before the make signal on the rising edge, and the break signal on the falling edge occurs before the make signal on the falling edge;
• and
• configuring the cross-coupled inverters to remove both the current source and the current sink from the load concurrently to allow tristate operation of the circuit.