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US 7,843,222 B1Granted
Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof
AssigneeEtron Technology, Inc.
InventorsChun Shiah, Tzu-Jen Ting, Yu-Hui Sung
Life of this patent
Estimating the term…
Abstract
A method for increasing responding speed and lifespan of a buffer includes detecting an edge of an input signal of the buffer, triggering a pulse signal with a predetermined period according to the detected edge, and driving the buffer for generating an output signal according to the pulse signal and the input signal.
Claims18
A buffer-driving circuit capable of increasing a responding speed of a buffer circuit and a lifespan of the buffer circuit, the buffer circuit having a transmitting transistor and a voltage-sharing transistor, the transmitting transistor coupled between a first voltage source and the voltage-sharing transistor, the voltage-sharing transistor coupled between the transmitting transistor and an output end of the buffer circuit, the first voltage source providing a first voltage, the buffer circuit utilized for buffering an input signal and accordingly generating an output signal from the output end of the buffer circuit, the buffer-driving circuit comprising:
- a level-shifting circuit, for shifting a voltage level of the input signal so as to generate a level-shifting signal;
- wherein when the voltage level of the input signal is equal to a first predetermined voltage level, the level-shifting signal is equal to the first voltage;
- when the voltage level of the input signal is equal to a second predetermined voltage level, the level-shifting signal is equal to a second voltage;
- a pulse generator, for generating a pulse signal with a predetermined period when the input signal is in a transition state;
- and
- a bias circuit, comprising:
- a first inverter, comprising:
- an input end, coupled to the level-shifting circuit, for receiving the level-shifting signal;
- an output end, coupled to a control end of the transmitting transistor, for outputting a transmitting gate-driving signal so as to control the transmitting transistor;
- a first power end, coupled to the first voltage source, for receiving the first voltage;
- and
- a second power end;
- and
- a second inverter, comprising:
- an input end, coupled to the pulse generator, for receiving the pulse signal;
- an output end, coupled to a control end of the voltage-sharing transistor and the second power end of the first inverter, for outputting a voltage-sharing gate-driving signal;
- a first power end, coupled to a second voltage source, for receiving the second voltage;
- and
- a second power end, coupled to a third voltage source, for receiving a third voltage;
- wherein an amplitude of the transmitting gate-driving signal is between the first voltage and the voltage-sharing gate-driving signal;
- wherein an amplitude of the voltage-sharing gate-driving signal is between the second voltage and the third voltage.
18 more elements
A buffer with a fast responding speed and a long life span for buffering an input signal so as to generate an output signal, the buffer comprising:
- a buffer circuit, comprising:
- a P-type buffer circuit, comprising:
- a P-type transmitting transistor, comprising:
- a first end, coupled to a first voltage source, for receiving a first voltage;
- a second end;
- and
- a control end, for receiving a P-type transmitting gate-driving signal;
- and
- a P-type voltage-sharing transistor, comprising:
- a first end, coupled to the second end of the P-type transmitting transistor;
- a second end, coupled to an output end of the buffer, for generating the output signal;
- and
- a control end, for receiving a P-type voltage-sharing gate-driving signal;
- and
- an N-type buffer circuit, comprising:
- an N-type transmitting transistor, comprising:
- a first end, coupled to a second voltage source, for receiving a second voltage;
- a second end;
- and
- a control end, for receiving an N-type transmitting gate-driving signal;
- and
- an N-type voltage-sharing transistor, comprising:
- a first end, coupled to the second end of the N-type transmitting transistor;
- a second end, coupled to the output end of the buffer, for generating the output signal;
- and
- a control end, for receiving an N-type voltage-sharing gate-driving signal;
- and
- a buffer-driving circuit, comprising:
- a P-type buffer-driving circuit, comprising:
- a P-type level-shifting circuit, for shifting a voltage level of the input signal so as to generate a P-type level shifting signal;
- wherein when the voltage level of the input signal is equal to a first predetermined voltage level, the P-type level shifting signal is equal to the first voltage;
- when the voltage level of the input signal is equal to a second predetermined voltage level, the P-type level-shifting signal is equal to a third voltage;
- a P-type pulse generator, for generating a P-type pulse signal with a first predetermined period according to a rising edge of the input signal;
- and
- a P-type bias circuit, comprising:
- a first inverter, comprising:
- an input end, coupled to the P-type level-shifting circuit, for receiving the P-type level-shifting signal;
- an output end, coupled to the control end of the P-type transmitting transistor, for outputting the P-type transmitting gate-driving signal;
- a first power end, coupled to the first voltage source, for receiving the first voltage;
- and
- a second power end;
- and
- a second inverter, comprising:
- an input end, coupled to the P-type pulse generator, for receiving the P-type pulse signal;
- an output end, coupled to the control end of the P-type voltage-sharing transistor and the second power end of the first inverter, for outputting the P-type voltage-sharing gate-driving signal;
- a first power end, coupled to a second voltage source, for receiving the second voltage;
- and
- a second power end, coupled to a third voltage source, for receiving the third voltage;
- and
- an N-type buffer-driving circuit, comprising:
- an N-type level-shifting circuit, for shifting the voltage level of the output signal so as to generating an N-type level-shifting signal;
- wherein when the voltage level of the input signal is equal to the first predetermined voltage level, the level-shifting signal is equal to a fourth voltage;
- when the voltage level of the input signal is equal to the second predetermined voltage level, the level-shifting signal is equal to the second voltage;
- an N-type pulse generator, for generating an N-type pulse signal with a second predetermined period according to a falling edge of the input signal;
- an N-type bias circuit, comprising:
- a third inverter, comprising:
- an input end, coupled to the N-type level-shifting circuit, for receiving the N-type level-shifting signal;
- an output end, coupled to the control end of the N-type transmitting transistor, for outputting the N-type transmitting gate-driving signal;
- a first power end, coupled to the second voltage source, for receiving the second voltage;
- and
- a second power end;
- and
- a fourth inverter, comprising:
- an input end, coupled to the N-type pulse generator, for receiving the N-type pulse signal;
- an output end, coupled to the control end of the N-type voltage-sharing transistor and the second power end of the third transistor, for outputting the N-type voltage-sharing gate-driving signal;
- a first power end, coupled to the first voltage source, for receiving the first voltage;
- and
- a second power end, coupled to a fourth voltage source, for receiving the fourth voltage;
- wherein an amplitude of the P-type transmitting gate-driving signal is between the first voltage and the P-type voltage-sharing gate-driving signal;
- wherein an amplitude of the P-type voltage-sharing gate-driving signal is between the second voltage and the third voltage;
- wherein an amplitude of the N-type transmitting gate-driving signal is between the second voltage and the N-type voltage-sharing gate-driving signal;
- wherein an amplitude of the N-type voltage-sharing gate-driving signal is between the first voltage and the fourth voltage.
69 more elements
Dependencies are inferred from the claim text.