Semiconductor device, display panel and electronic equipment

A display panel having a pixel array section and its drive circuits formed on an insulating substrate using single-channel type thin film transistors, wherein

• some of the drive circuits have a buffer circuit,
• the buffer circuit has an output stage which comprises first and second thin film transistors connected in series between first and second power sources, and
• the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor, wherein the buffer circuit has a first input stage whose output terminal potential is switched in a complementary manner by the input timings of the set and reset signals,
• wherein the buffer circuit has a second input stage whose output terminal potential is switched in a complementary manner by the input timings of the set and reset signals and whose output terminal potential changes in opposite phase with the output terminal potential of the first input stage, and
• wherein the output terminal potentials of the first and second input stages are used as the set and reset signals of the output stage.

Electronic equipment comprising:

• a display panel having a pixel array section and its drive circuits formed on an insulating substrate using single-channel type thin film transistors;
• a system control section;
• and
• an operation input section for the system control section, wherein
• some of the drive circuits have a buffer circuit,
• the buffer circuit has an output stage which includes first and second thin film transistors connected in series between first and second power sources, and
• the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor,
• wherein the buffer circuit has a first input stage whose output terminal potential is switched in a complementary manner by the input timings of the set and reset signals,
• wherein the buffer circuit has a second input stage whose output terminal potential is switched in a complementary manner by the input timings of the set and reset signals and whose output terminal potential changes in opposite phase with the output terminal potential of the first input stage, and
• wherein the output terminal potentials of the first and second input stages are used as the set and reset signals of the output stage.