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US 7,843,219 B2Granted
XOR logic circuit
AssigneeHynix Semiconductor Inc.
InventorJin-Yeong Moon
Life of this patent
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Abstract
An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.
Claims18
An XOR logic circuit, comprising:
- a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals;
- a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the second input terminal;
- and
- a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first input terminal.
1 more element
An XOR logic circuit, comprising:
- a first PMOS transistor configured to have a source-drain path formed between a first input terminal and an output terminal and a gate coupled to a second input terminal;
- a second PMOS transistor configured to have a source-drain path formed between the second input terminal and the output terminal and a gate coupled to the first input terminal;
- a first NMOS transistor configured to have a source-drain path formed between the output terminal and the first input terminal and a gate coupled to a common node;
- a second NMOS transistor configured to have a source-drain path formed between the output terminal and the common node and a gate coupled to the first input terminal;
- a third PMOS transistor configured to have a source-drain path formed between a power voltage terminal and the common node and a gate coupled to the second input terminal;
- and
- a third NMOS transistor configured to have a source-drain path formed between a ground voltage terminal and the common node and a gate coupled to the second input terminal.
4 more elements
Dependencies are inferred from the claim text.