Data latch with structural hold
AssigneeFreescale Semiconductor, Inc.
InventorsRavindraraj Ramaraju, David R. Bearden, Cody B. Croxton, Prashant U. Kenkare
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AssigneeFreescale Semiconductor, Inc.
InventorsRavindraraj Ramaraju, David R. Bearden, Cody B. Croxton, Prashant U. Kenkare
Estimating the term…
A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
A data storage circuit, comprising:
A method for operating a master latch which is connected in series with a slave latch using a single input clock to provide multiplexed data flip flop (MUX DFF) behavior during a functional mode and level sensitive scan design (LSSD) behavior during a scan mode, comprising:
A system for propagating data in a datapath, comprising:
Dependencies are inferred from the claim text.