US 7,843,217 B2Granted

Shift register and semiconductor display device

AssigneeSemiconductor Energy Laboratories Co., Ltd.

InventorsMitsuaki Osame, Aya Anzai

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Abstract

The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Claims9

Dependent claims

A shift register comprising:

a plurality of stages of first circuits each of which includes a circuitry, said circuitry comprising:
a first circuit comprising a first transistor;
and a second transistor;
a second circuit comprising a third transistor and a fourth transistor;
and
a third circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first terminal of the circuitry,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second power source,
wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the third transistor is electrically connected to a second terminal,
wherein a first terminal of the switching element is input with a clock signal,
wherein a second terminal of the switching element is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a third terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fourth terminal, and
wherein a third terminal of the switching element is electrically connected to a fifth terminal.

19 more elements

A shift register comprising:

a plurality of stages of first flip-flop circuits each of which includes a circuitry, said circuitry comprising:
a first circuit comprising a first transistor;
and a second transistor electrically connected to the first transistor in series;
a second circuit comprising a third transistor and a fourth transistor;
and
a third circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first terminal of the circuitry,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second power source,
wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the third transistor is electrically connected to a second terminal,
wherein a first terminal of the switching element is input with a clock signal,
wherein a second terminal of the switching element is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a third terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fourth terminal, and
wherein a third terminal of the switching element is electrically connected to a fifth terminal.

19 more elements

A shift register comprising:

a plurality of stages of first flip-flop circuits each of which includes a circuitry, said circuitry comprising:
a first circuit comprising a first transistor;
and a second transistor electrically connected to the first transistor in series;
a second circuit comprising a third transistor and a fourth transistor;
and
a third circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first terminal of the circuitry,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second power source,
wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the third transistor is electrically connected to a second terminal,
wherein a gate of the fifth transistor is electrically connected to a third terminal,
wherein a first terminal of the switching element is inputted with a clock signal,
wherein a second terminal of the switching element is electrically connected to the other of the source and the drain of the fifth transistor,
wherein the second terminal of the switching element is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, and
wherein a third terminal of the switching element is electrically connected to a fifth terminal.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/565,796Filed 24 Sep 2009 · continuation
Priority: JP 2004-17619914 Jun 2004
Published: US 2010/0034338 A111 Feb 2010
Granted: 30 Nov 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only
G09G 3/3266
Organic, e.g. using organic light-emitting diodes [OLED]: details of drivers for scan electrodes
G09G 3/3275
Organic, e.g. using organic light-emitting diodes [OLED]: details of drivers for data electrodes
G09G 3/3688
Details of drivers for data electrodes: suitable for active matrices only

Family

PCT/JP2005/011096Parent of this continuation · filed 10 Jun 2005
US 2010/0034338 A1Pre-grant publication · published 11 Feb 2010
Application11/629,091Parent of this continuation
US 7,602,215 B2Parent of this continuation
US 2008/0273004 A1Published application
US 7,843,217 B2This patent

From the US filing history. Foreign family members aren’t listed.