Impedance adjusting circuit and semiconductor memory device having the same
AssigneeHynix Semiconductor Inc.
InventorsKi-Ho Kim, Seok-Cheol Yoon
Life of this patent
Estimating the term…
Abstract
An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section; and a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes.
Claims31
An impedance adjusting circuit, comprising:
- a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance;
- a transmission line circuit configured to receive the first and second calibration codes from the calibration circuit, to transfer the first calibration code through transmission lines during a first section and to transfer the second calibration code through the transmission lines during a second section;
- and
- a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes,
- wherein the first and second calibration codes share the transmission lines while the first and second calibration codes are transferred to the termination resistor circuit.
A semiconductor memory device, comprising:
- a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance;
- a transmission line circuit configured to receive the first and second calibration codes, to transfer the first calibration code through transmission lines during a first section and to transfer the second calibration code through the transmission lines during a second section;
- and
- an output driver configured to pull-up terminate or pull-down terminate an output node with resistance determined by receiving the first and second calibration codes, and output data,
- wherein the first and second calibration codes share the transmission lines while the first and second calibration codes are transferred to the output driver.
A semiconductor memory device, comprising:
- a calibration circuit configured to generate N bits of first calibration code and N bits of second calibration code for determining termination resistance;
- a transmission line circuit configured to receive the N bits of first and second calibration codes, to transfer the N bits of first calibration code through N number of transmission lines during a first duration and to transfer the N bits of second calibration code through the N number of transmission lines during a second duration;
- and
- an output driver configured to pull-up terminate or pull-down terminate an output node with resistance determined by receiving the N bits of first and second calibration codes, and output data,
- wherein the N bits of first and second calibration codes share the N number of transmission lines while the N bits of first and second calibration codes are transferred to the output driver, and
- wherein the N is natural number.
Dependencies are inferred from the claim text.