Stack package made of chip scale packages
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Ho Lee
Life of this patent
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Abstract
A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.
Claims20
A stack package including two or more area array type chip scale packages comprising:
- a lower chip scale package of an adjacent pair of chip scale packages, the lower chip scale package comprising a substrate, a plurality of ball land pads formed on a first surface of the substrate, circuit patterns terminating in a plurality of connecting pads formed outside an area in which the plurality of ball land pads are formed, wherein the circuit patterns and the plurality of connecting pads are formed on the first surface of the substrate and are electrically connected to the plurality of ball land pads, and a chip installed on a second surface of the substrate and electrically connected to the circuit patterns, wherein the second surface is opposite the first surface;
- and
- an upper chip scale package of the adjacent pair of chip scale packages, the upper chip scale package comprising a substrate, a plurality of ball land pads formed on a first surface of the substrate, circuit patterns terminating in a plurality of connecting pads formed outside an area in which the plurality of ball land pads are formed, wherein the circuit patterns and the plurality of connecting pads are formed on the first surface of the substrate and are electrically connected to the plurality of ball land pads, and a chip installed on a second surface of the substrate and electrically connected to the circuit patterns, wherein the second surface is opposite the first surface,
- wherein the upper chip scale package is stacked on the lower chip scale package so that the ball land pads of the upper chip scale package face a direction opposite that of the ball land pads of the lower chip scale package, and wherein the circuit patterns of the upper chip scale package are electrically connected to the circuit patterns of the lower chip scale package.
The stack package according to 7, wherein one of the adjacent pair of chip scale packages is attached to the other by an adhesive applied on the first encapsulating part.
A stack package including two or more area array type chip scale packages comprising:
- a lower chip scale package of an adjacent pair of chip scale packages, the lower chip scale package comprising a substrate, a plurality of ball land pads formed on a first surface of the substrate, circuit patterns terminating in a plurality of connecting pads formed outside an area in which the plurality of ball land pads are formed, wherein the circuit patterns and the plurality of connecting pads are formed on the first surface of the substrate and are electrically connected to the plurality of ball land pads, and a chip installed on a second surface of the substrate and electrically connected to the circuit patterns, wherein the second surface is opposite the first surface;
- and
- an upper chip scale package of the adjacent pair of chip scale packages, the upper chip scale package comprising a substrate, a plurality of ball land pads formed on a first surface of the substrate, circuit patterns terminating in a plurality of connecting pads formed outside an area in which the plurality of ball land pads are formed, wherein the circuit patterns and the plurality of connecting pads are formed on the first surface of the substrate and are electrically connected to the plurality of ball land pads, and a chip installed on a second surface of the substrate and electrically connected to the circuit patterns, wherein the second surface is opposite the first surface,
- wherein the upper chip scale package is stacked on the lower chip scale package so that the ball land pads of the upper chip scale package face a direction opposite that of the ball land pads of the lower chip scale package, and wherein the circuit patterns of the upper chip scale package are electrically connected to the circuit patterns of the lower chip scale package via one or more conductive vias.
Dependencies are inferred from the claim text.