Method and structure for improving device performance variation in dual stress liner technology

A semiconductor structure comprising:

• a semiconductor substrate having at least one dummy gate region in proximity to at least one nFET;
• and
• a tensile stress liner and a compressive stress liner located on said substrate, wherein said tensile stress liner covers the at least one nFET and is present in part over said at least one dummy gate region such that an boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

A semiconductor structure comprising:

• a semiconductor substrate having at least one dummy gate region in proximity to at least one pFET;
• and
• a tensile stress liner and a compressive stress liner located on said substrate, wherein said compressive stress liner covers the at least one pFET and is present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

A semiconductor structure comprising:

• a semiconductor substrate having at least one dummy gate region in proximity to at least one active gate region;
• and
• a tensile stress liner and a compressive stress liner located on said substrate, wherein said tensile stress liner and said compressive stress liner are present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.

A method of forming a semiconductor structure comprising:

• providing a semiconductor substrate having at least one dummy gate region in proximity to at least one active gate region;
• and
• disposing, in any order, a tensile stress liner and a compressive stress liner on said substrate, wherein said tensile stress liner and said compressive stress liner are present in part over said at least one dummy gate region such that a boundary or gap exists between the stress liners that lands on top of said at least one dummy gate region.