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AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Andres Bryant, William F. Clark, Jr., Edward J. Nowak
Estimating the term…
Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor structure comprising:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor structure comprising:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising a field effect transistor structure comprising:
Dependencies are inferred from the claim text.