Metal high-k transistor having silicon sidewall for reduced parasitic capacitance

A metal high dielectric constant (MHK) transistor, comprising:

• a substrate;
• a MHK gate structure disposed on the substrate between a source region and a drain region, the MHK gate structure comprising a layer of high dielectric constant material and an overlying layer comprised of a metal, the MHK gate structure further having an overlying layer comprised of silicon, where a lateral extent of the layer of high dielectric constant material is greater than lateral extents of the overlying layer comprised of metal and the overlying layer comprised of silicon;
• a single sidewall layer comprised of silicon disposed on sidewalls of the MHK gate structure to cover sidewalls of the overlying layer comprised of metal and sidewalls of the overlying layer comprised of silicon, said single sidewall layer also being disposed over a top surface of the layer of high dielectric constant material;
• and
• an offset spacer layer disposed over and physically in contact with exposed portions of the single sidewall layer and exposed portions of the layer of high dielectric constant material, wherein the offset spacer layer has a thickness in a range of about three to six nanometers.