Fully isolated high-voltage MOS device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-San Wei, Kuo-Ming Wu, Yi-Chun Lin
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Abstract
A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.
Claims20
A semiconductor structure comprising:
- a semiconductor substrate;
- an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate;
- a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate;
- and
- a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.
A semiconductor structure comprising:
- a semiconductor substrate;
- a first high-voltage n-well (HVNW) region in the semiconductor substrate;
- a second HVNW region in the semiconductor substrate, wherein the first and the second HVNW regions are parallel;
- a third HVNW region between the first and the second HVNW regions;
- a first high-voltage p-well (HVPW) region between the first and the second HVNW regions;
- a first and a second n-type isolation (N-ISO) region underlying and adjoining the first and the second HVNW regions, respectively;
- an n-type buried layer (NBL) connecting the first and the second N-ISO regions;
- and
- a p-type buried layer (PBL) on the NBL.
A semiconductor structure comprising:
- a semiconductor substrate of a p-type conductivity;
- an epitaxial layer on the semiconductor substrate;
- an n-type buried layer (NBL) extending from the semiconductor substrate into the epitaxial layer;
- a p-type buried layer (PBL) on the NBL;
- an n-type isolation region (N-ISO) ring extending from the semiconductor substrate into the epitaxial layer, wherein the N-ISO ring encircles and adjoins the NBL and at least a portion of the PBL;
- a high-voltage n-well (HVNW) ring on and adjoining the N-ISO ring;
- and
- a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL, wherein a portion of the HVNMOS device in the epitaxial layer is encircled by the HVNW ring.
Dependencies are inferred from the claim text.