Gate electrode structure, MOS field effect transistors and methods of manufacturing the same
AssigneeQimonda AG
InventorsStefan Jakschik, Thomas Hecht
Life of this patent
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Abstract
A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.
Claims22
An integrated circuit including a transistor, the transistor comprising a gate electrode structure, comprising:
- a plurality of bi-layers, each of the bi-layers including:
- a plating film comprising a polycrystalline material;
- and
- a stress amplifier film configured to affect a crystalline structure of the polycrystalline material, the stress amplifier film having a thickness between 2 to 10 nanometers, wherein:
- the bi-layers are arranged to form a laminated film stack with alternating stress amplifier and plating films;
- and
- the stress amplifier film of an upper bi-layer is in contact with the plating film of a lower bi-layer and is in contact with the plating film of the upper bi-layer.
An electronic system, comprising an integrated circuit, the integrated circuit including:
- a transistor comprising:
- a gate dielectric film;
- a conductive electrode film;
- and
- a gate electrode structure including:
- a plurality of bi-layers, each of the bi-layers including:
- a plating film including a polycrystalline material;
- and
- a stress amplifier film configured to affect a crystalline structure of the polycrystalline material, wherein:
- the bi-layers are arranged to form a laminated film stack with alternating stress amplifier and plating films;
- and
- the conductive electrode film is disposed between the gate dielectric film and one of the stress amplifier films and is in contact with the gate dielectric film and the one of the stress amplifier films, respectively.
An integrated circuit including a transistor, the transistor comprising a gate electrode structure, the gate electrode structure comprising:
- a plurality of bi-layers, each of the bi-layers including:
- a plating film comprising a polycrystalline material;
- and
- a stress amplifier film that is configured to cause a stress at an interface between the plating film and the stress amplifier film, resulting in a strain in the stress amplifier film;
- wherein the stress amplifier film comprises amorphous carbon.
An integrated circuit including a transistor, the transistor comprising a gate electrode structure, the gate electrode structure comprising:
- at least two bi-layers, each bi-layer including:
- a plating film comprising a polycrystalline material;
- and
- a stress amplifier film, wherein the bi-layers are arranged to form a laminated film stack with alternating stress amplifier and plating films, the stress amplifier film of an upper bi-layer being in contact with the plating film of a lower bi-layer and being in contact with the plating film of the upper bi-layer.
Dependencies are inferred from the claim text.