Flip chip semiconductor die internal signal access system and method
AssigneeNVIDIA Corporation
InventorsBrian S. Schieck, Howard Lee Marks
Life of this patent
Estimating the term…
Abstract
A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
Claims13
A semiconductor die comprising:
- means for transmitting test signals off of said semiconductor die;
- means for communicating said test signals to said means for transmitting test signals off of said semiconductor die, wherein said means for communicating said test signals to said means for transmitting test signals off of said semiconductor die is routed in a spiral pattern included in a redistribution layer and said means for communicating said test signals to said means for transmitting test signals off of said semiconductor die is disposed such that multiple test signals are accessible at varying degrees of electronic component granularity within said die and along said means for communicating said test signals to said means for transmitting test signals off of said semiconductor die, said means for communicating said test signals to said means for transmitting test signals off of said semiconductor die communicatively coupled to said means for transmitting test signals off of said semiconductor die;
- and
- means for accessing said test signals in said semiconductor die and for electrical coupling a conductor to said redistribution layer.
A semiconductor device comprising:
- means for communicating test signals on an external access point, wherein said means for communicating test signals on an external access point is a package substrate;
- and
- a semiconductor die having test probe points accessible by said external access point, wherein said semiconductor die is electrically coupled to said package substrate, wherein said semiconductor die comprises:
- means for transmitting internal test signals off of said semiconductor die to said package substrate, wherein said means for transmitting internal test signals off of said semiconductor die to said package substrate is a conductive test signal bump, said conductive test signal bump is located on a first surface of said semiconductor die and electrically coupled to a test signal redistribution layer trace;
- means for communicating internal signals to said conductive test signal bump, wherein said means for communicating internal signals to said conductive test signal bump includes said test signal redistribution layer trace, wherein said test signal redistribution layer trace is routed in a spiral pattern included in a redistribution layer and said test signal redistribution layer trace is disposed such that multiple test signals are accessible at varying degrees of electronic component granularity within said die and along said test signal redistribution layer trace, said test signal redistribution layer trace communicatively coupled said conductive test signal bump;
- means for accessing test signals in said semiconductor die and for electrical coupling to said signal redistribution layer, wherein said means for accessing test signals in said semiconductor die and for electrical coupling to said signal redistribution layer is a test probe point;
- and
- means for electrically coupling said test probe point to said signal redistribution layer, wherein said means for electrically coupling said test probe point to said signal redistribution layer is a test access via.
Dependencies are inferred from the claim text.