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US 7,842,597 B2Granted
Chip package, chip packaging, chip carrier and process thereof
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorYu-Pin Tsai
Life of this patent
Estimating the term…
Abstract
A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.
Claims23
A chip packaging process, comprising:
- providing a semiconductor substrate having a first surface and a second surface;
- forming a plurality of blind vias on the second surface of the semiconductor substrate;
- forming a plurality of conductive plugs inside the blind vias, wherein an end of each conductive plug is exposed out of the blind via;
- lapping the first surface of the semiconductor substrate for exposing another end of each conductive plug;
- after lapping the semiconductor substrate, performing a dicing process to the semiconductor substrate;
- after the dicing process, disposing a plurality of chips on the first surface of the semiconductor substrate, wherein each chip is electrically connected to the corresponding conductive plug;
- and
- forming a plurality of solder balls on the semiconductor substrate, wherein the solder balls are disposed on the second surface of the semiconductor substrate, while the solder balls are electrically connected to the conductive plugs.
5 more elements
A chip packaging process, comprising:
- providing a semiconductor substrate having a first surface and a second surface;
- forming a plurality of blind vias on the second surface of the semiconductor substrate;
- forming a plurality of conductive plugs inside the blind vias, wherein an end of each conductive plug is exposed out of the blind via;
- lapping the first surface of the semiconductor substrate for exposing another end of each conductive plug;
- disposing a plurality of chips on the first surface of the semiconductor substrate, wherein each chip is electrically connected to the corresponding conductive plug by forming a plurality of bumps on the chips or the semiconductor substrate, wherein each chip is electrically connected to the corresponding conductive plug via the corresponding bump;
- after disposing the chips, performing a dicing process to the semiconductor substrate;
- after the dicing process, forming an underfill between the chips and the semiconductor substrate for encapsulating the bumps;
- and
- forming a plurality of solder balls on the semiconductor substrate, wherein the solder balls are disposed on the second surface of the semiconductor substrate, while the solder balls are electrically connected to the conductive plugs.
6 more elements
A chip packaging process, comprising:
- providing a semiconductor substrate having a first surface and a second surface;
- forming a plurality of blind vias on the second surface of the semiconductor substrate;
- forming a plurality of conductive plugs inside the blind vias, wherein an end of each conductive plug is exposed out of the blind via;
- lapping the first surface of the semiconductor substrate for exposing another end of each conductive plug;
- disposing a plurality of chips on the first surface of the semiconductor substrate, wherein each chip is electrically connected to the corresponding conductive plug by forming a plurality of bumps on the chips or the semiconductor substrate, wherein each chip is electrically connected to the corresponding conductive plug via the corresponding bump;
- after disposing the chips, forming an underfill between the chips and the semiconductor substrate for encapsulating the bumps;
- after forming the underfill, performing a dicing process to the semiconductor substrate;
- and
- after the dicing process, forming a plurality of solder balls on the semiconductor substrate, wherein the solder balls are disposed on the second surface of the semiconductor substrate, while the solder balls are electrically connected to the conductive plugs.
6 more elements
Dependencies are inferred from the claim text.